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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 123 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20 mhz ? high endurance non-volatile memory segments ? 2/4/8k bytes of in-system self-p rogrammable flash program memory ? endurance: 10,000 write/erase cycles ? 128/256/512 by tes of in-system programmable eeprom ? endurance: 100,000 write/erase cycles ? 128/256/512 bytes of internal sram ? data retention: 20 years at 85c / 100 years at 25 c ? in-system programmable via spi port ? programming lock for software security ? peripheral features ? one 8/16-bit timer/counter with prescaler ? one 8/10-bit high speed ti mer/counter with prescaler ? 3 high frequency pwm outputs with separate output compare registers ? programmable dead time generator ? 10-bit adc ? 11 single-ended channels ? 16 differential adc channel pairs ? 15 differential adc channel pairs with programmable gain (1x, 8x, 20x, 32x) ? on-chip analog comparator ? programmable watchdog timer with separate on-chip oscillator ? universal serial interface with start condition detector ? interrupt and wake-up on pin change ? special microcontroller features ? debugwire on-chip debug system ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? four sleep modes: low power idle, adc noise reduction, standby and power- down ? on-chip temperature sensor ? i/o and packages ? 16 programmable i/o lines ? 20-pin pdip, 20-pin soic, 20- pin tssop and 32-pad mlf ? operating voltage ? 1.8 ? 5.5v ? speed grades ? 0 ? 4 mhz @ 1.8 ? 5.5v ? 0 ? 10 mhz @ 2.7 ? 5.5v ? 0 ? 20 mhz @ 4.5 ? 5.5v ? power consumption at 1 mhz, 1.8v, 25c ? active: 200 a ? power-down mode: 0.1 a 8-bit microcontroller with 2/4/8k bytes in-system programmable flash attiny261a attiny461a attiny861a 8197c?avr?05/11
2 8197c?avr?05/11 attiny261a/461a/861a 1. pin configurations figure 1-1. pinout attiny261a/461a/861a note: to ensure mechanical stability the center pad underneath the qfn/mlf package should be soldered to ground on the board. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 (mosi/di/sda/oc1a/pcint8) pb0 (miso/do/oc1a/pcint9) pb1 (sck/usck/scl/oc1b/pcint10) pb2 (oc1b/pcint11) pb3 vcc gnd (adc7/oc1d/clki/xtal1/pcint12) pb4 (adc8/oc1d/clko/xtal2/pcint13) pb5 (adc9/int0/t0/pcint14) pb6 (adc10/reset/pcint15) pb7 pa0 (adc0/di/sda/pcint0) pa1 (adc1/do/pcint1) pa2 (adc2/int1/usck/scl/pcint2) pa3 (aref/pcint3) agnd avcc pa4 (adc3/icp0/pcint4) pa5 (adc4/ain2/pcint5) pa6 (adc5/ain0/pcint6) pa7 (adc6/ain1/pcint7) pdip/soic/tssop 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 nc (oc1b/pcint11) pb3 nc vcc gnd nc (adc7/oc1d/clki/xtal1/pcint12) pb4 (adc8/oc1d/clko/xtal2/pcint13) pb5 nc pa2 (adc2/int1/usck/scl/pcint2) pa3 (aref/pcint3) agnd nc nc avcc pa4 (adc3/icp0/pcint4) nc (adc9/int0/t0/pcint14) pb6 (adc10/reset/pcint15) pb7 nc (adc6/ain1/pcint7) pa7 (adc5/ain0/pcint6) pa6 (adc4/ain2/pcint5) pa5 nc pb2 (sck/usck/scl/oc1b/pcint10) pb1 (miso/do/oc1a/pcint9) pb0 (mosi/di/sda/oc1a/pcint8) nc nc nc pa0 (adc0/di/sda/pcint0) pa1 (adc1/do/pcint1) qfn/mlf 3 8197c?avr?05/11 attiny261a/461a/861a 1.1 pin descriptions 1.1.1 vcc supply voltage. 1.1.2 gnd ground. 1.1.3 avcc analog supply voltage. this is the supply voltage pin for the analog-to-digital converter (adc), the analog comparator, the brown-out detector (bod), the internal voltage reference and port a. it should be externally connected to vcc, even if some peripherals such as the adc are not used. if the adc is used avcc should be connected to vcc through a low-pass filter. 1.1.4 agnd analog ground. 1.1.5 port a (pa7:pa0) an 8-bit, bi-directional i/o port with internal pull-up resistors, individually selectable for each bit. output buffers have symmetrical drive characteri stics with both high sink and source capability. as inputs, port pins that are externally pulled low will source current if pull-up resistors have been activated. port pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the device, as listed on page 62 . 1.1.6 port b (pb7:pb0) an 8-bit, bi-directional i/o port with internal pull-up resistors, individually selectable for each bit. output buffers have symmetrical drive characteri stics with both high sink and source capability. as inputs, port pins that are externally pulled low will source current if pull-up resistors have been activated. port pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the device, as listed on page 65 . 1.1.7 reset reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and prov ided the reset pin has not been disabled. the min- imum pulse length is given in table 19-4 on page 188 . shorter pulses are not guaranteed to generate a reset. the reset pin can also be used as a (weak) i/o pin. 4 8197c?avr?05/11 attiny261a/461a/861a 2. overview attiny261a/461a/861a are low-power cmos 8-bit microcontrollers based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the devices achieve throughputs approaching 1 mips per mhz allowing the system designer to opti- mize power consumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. port a (8) port b (8) usi timer/counter1 timer/counter0 a/d conv. internal bandgap analog comp. sram flash eeprom watchdog oscillator watchdog timer oscillator circuits / clock generation power supervision por / bod & reset vcc gnd program logic debugwire agnd aref avcc databus pa[0:7] pb[0:7] 11 reset xtal[1:2] cpu 3 5 8197c?avr?05/11 attiny261a/461a/861a the attiny261a/461a/861a provides the following features: 2/4/8k byte of in-system program- mable flash, 128/256/512 by tes eeprom, 128/256/512 bytes sram, 16 general purpose i/o lines, 32 general purpose working registers, an 8-bit timer/counter with compare modes, an 8- bit high speed timer/counter, a universal serial interface, internal and external interrupts, an 11-channel, 10-bit adc, a progra mmable watchdog timer with inter nal oscillator, and four soft- ware selectable power saving modes. idle mode stops the cpu while allowing the sram, timer/counter, adc, analog comparator, and interrupt system to continue functioning. power- down mode saves the register contents, disabling all chip functions until the next interrupt or hardware reset. adc noise reduction mode stops the cpu and all i/o modules except adc, to minimize switching noise during adc conver sions. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allo wing very fast start-up combined with low power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be re-programmed in-system through an spi serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the avr core. the attiny261a/461a/861a avr is supported by a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, and evaluation kits. 6 8197c?avr?05/11 attiny261a/461a/861a 3. general information 3.1 resources a comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in the extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically, this means ?lds? and ?sts? combined with ?sbrs?, ?s brc?, ?sbr?, and ?cbr?. note that not all avr devices include an extended i/o map. 3.3 capacitive touch sensing atmel qtouch library provides a simple to use solution for touch sensitive interfaces on atmel avr microcontrollers. the qtouch library includes support for qtouch ? and qmatrix ? acquisi- tion methods. touch sensing is easily added to any application by linking the qtouch library and using the application programming interface (api) of the library to define the touch channels and sensors. the application then calls the api to retrieve channel information and determine the state of the touch sensor. the qtouch library is free and can be downloaded from the atmel website. for more informa- tion and details of implementation, refer to the qtouch library user guide ? also available from the atmel website. 3.4 data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 7 8197c?avr?05/11 attiny261a/461a/861a 4. cpu core this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 architectural overview figure 4-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 8 8197c?avr?05/11 attiny261a/461a/861a the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the to tal sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. 4.2 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 4.3 status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is neither automaticall y stored when entering an interrupt routine, nor restored when returning from an interrupt. this must be handled by software. 9 8197c?avr?05/11 attiny261a/461a/861a 4.3.1 sreg ? avr status register ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for th e interrupts to be enabled. the individual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operation s. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 10 8197c?avr?05/11 attiny261a/461a/861a 4.4 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 4-2 below shows the structure of the 32 general purpose working registers in the cpu. figure 4-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 4-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 4.4.1 the x-register, y-register, and z-register the registers r26:r31 have some added functions to their general purpose usage. these regis- ters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 4-3 . figure 4-3. the x-, y-, and z-registers 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 11 8197c?avr?05/11 attiny261a/461a/861a in different addressing modes these address registers function as automatic increment and automatic decrement (see the instruction set reference for details). 4.5 stack pointer the stack is mainly used for storing temporary data, local variables and return addresses for interrupts and subroutine calls. the stack pointer register always points to the top of the stack, in the data sram stack area where the subroutine and interrupt stacks are located. the stack in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above start of the sram (see figure 5-2 on page 16 ). the initial stack pointer value equals the last address of the internal sram. note that the stack is implemented as growing from higher to lower memory locations. this means a stack push command decreases the stack pointer. see table 4-1 . the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementations of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 4.5.1 sph and spl ? stack pointer register 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7070 r31 (0x1f) r30 (0x1e) table 4-1. stack pointer instructions instruction stack pointer description push decremented by 1 data is pushed onto the stack icall rcall decremented by 2 return address is pushed onto the stack with a subroutine call or interrupt pop incremented by 1 data is popped from the stack ret reti incremented by 2 return address is popped from the stack with return from subroutine or return from interrupt bit 151413121110 9 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend 12 8197c?avr?05/11 attiny261a/461a/861a 4.6 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-4. the parallel instruction fetches and instruction executions figure 4-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 4-5. single cycle alu operation 4.7 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 49 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 13 8197c?avr?05/11 attiny261a/461a/861a priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt fl ag will be set and remember ed until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is clea red, the corres ponding interrupt fl ag(s) will be set and remembered until the global interrupt enable bit is set, and will then be exec uted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction before any pending interrupt is served. note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. note: see ?code examples? on page 6 . assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 15 8197c?avr?05/11 attiny261a/461a/861a 5. memories this section describes the different memories of the attiny261a/461a/861a. the avr architec- ture has two main memory spaces, the data memory and the program memory space. in addition, the attiny261a/461a/861a features an eeprom memory for data storage. all three memory spaces are linear and regular. 5.1 in-system re-programmable flash program memory the attiny261a/461a/861a contains 2/4/8k by te on-chip in-system reprogrammable flash memory for program storage. since all avr instructions are 16 or 32 bits wide, the flash is orga- nized as 1024/2048/4096 x 16. the flash memory has an endurance of at least 10,000 write/erase cycles. the attiny261a/461a/861a program counter (pc) is 10/11/12 bits wide, thus capable of addressing the 1024/2048/4096 program memory locations. ?memory programming? on page 168 contains a detailed description on flash data serial downloading using the spi pins. constant tables can be allocated within the entire address space of program memory (see the lpm ? load program memory instruction description). timing diagrams for instruction fetch and execution are presented in ?instruction execution tim- ing? on page 12 . figure 5-1. program memory map 5.2 sram data memory figure 5-2 on page 16 shows how the attiny261a/461a/861a sram memory is organized. the lower data memory locations address both the register file, the i/o memory and the inter- nal data sram. the first 32 locations address the register file, the next 64 locations the standard i/o memory, and the last 128/256/512 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. 0x0000 0x03ff/0x07ff/0x0fff program memory 16 8197c?avr?05/11 attiny261a/461a/861a when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o registers, and the 128/256/512 bytes of inter- nal data sram in the attiny261a/461a/861a are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 10 . figure 5-2. data memory map 5.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as illustrated in figure 5-3 . figure 5-3. on-chip data sram access cycles 5.3 eeprom data memory the attiny261a/461a/861a cont ains 128/256/512 byte s of data eeprom memory. it is orga- nized as a separate data spac e, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specif ying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of serial data downloading to the eeprom, see ?electrical characteristics? on page 185 . 32 registers 64 i/o registers internal sram (128/256/512 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x0df/0x15f/0x25f 0x0060 data memory clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 17 8197c?avr?05/11 attiny261a/461a/861a 5.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access times for the eeprom are given in table 5-1 on page 22 . a self-timing func- tion, however, lets the user software detect when the next byte can be written. if the user code contains instructions that write the eeprom, so me precautions must be taken. in heavily fil- tered power supplies, v cc is likely to rise or fall slo wly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom corruption? on page 19 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to ?atomic byte programming? on page 17 and ?split byte programming? on page 17 for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is written, the cp u is halted for two clock cycles before the next instruction is executed. 5.3.2 atomic byte programming using atomic byte programming is the simplest mode. when writing a by te to the eeprom, the user must write the address in to the eearl register and data into eedr register. if the eepmn bits are zero, writing eepe (within four cycles after eem pe is written) will trigger the erase/write operation. both the erase and write cycle are done in one operation and the total programming time is given in table 5-1 on page 22 . the eepe bit remains set until the erase and write operations are completed. while the devi ce is busy with programm ing, it is not possi- ble to do any other eeprom operations. 5.3.3 split byte programming it is possible to split the erase and write cycle in two different operations. this may be useful if the system requires short access time for some limited period of ti me (typically if the power sup- ply voltage falls). in order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. but since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after power-up). 5.3.4 erase to erase a byte, the address must be written to eear. if the eepmn bits are 0b01, writing the eepe within four cycles after eempe is written will trigger the erase operation only (program- ming time is given in table 5-1 on page 22 ). the eepe bit remains se t until the erase operation completes. while the device is busy programming, it is not possible to do any other eeprom operations. 5.3.5 write to write a location, the user must write the address into eear and the data into eedr. if the eepmn bits are 0b10, writing the eepe (within f our cycles after eempe is written) will trigger the write operation only (programming time is given in table 5-1 on page 22 ). the eepe bit remains set until the write operation completes. if the location to be written has not been erased before write, the data that is stored must be considered as lost. while the device is busy with programming, it is not possible to do any ot her eeprom operations. 18 8197c?avr?05/11 attiny261a/461a/861a the calibrated oscillator is used to time the eeprom accesses. make sure the oscillator fre- quency is within the requirements described in ?osccal ? oscillator ca libration register? on page 32 . 5.3.6 program examples the following code examples show one assembly and one c function for erase, write, or atomic write of the eeprom. the examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during ex ecution of th ese functions. note: see ?code examples? on page 6 . assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set programming mode ldi r16, (0< 21 8197c?avr?05/11 attiny261a/461a/861a 5.5.2 eearl ? eeprom address register ? bit 7 ? eear7: eeprom address this is the most significant eeprom address bit of attiny461 a. in devices with less eeprom, i.e. attiny261a, this bit is re served and will always read zero. the initial value of the eeprom address register (eear) is undefined and a proper value must therefore be written before the eeprom is accessed. ? bits 6:0 ? eear[6: 0]: eeprom address these are the (low) bits of the eeprom a ddress register. the eeprom data bytes are addressed linearly in the range 0 ... 128/256/512. the initial valu e of eear is undefined and a proper value must be therefore be written before the eeprom may be accessed. 5.5.3 eedr ? eeprom data register ? bits 7:0 ? eedr[7:0]: eeprom data for the eeprom write operation the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 5.5.4 eecr ? eeprom control register ? bit 7 ? res: reserved bit this bit is reserved for future use and will always read zero. for compatibility with future avr devices, always write this bit to zero. after reading, mask out this bit. ? bit 6 ? res: reserved bit this bit is reserved and will always read as zero. ? bits 5:4 ? eepm[1:0]: eepr om programming mode bits the eeprom programming mode bits setting defines which programming action that will be triggered when writing eepe. it is possible to program data in one atomic operation (erase the bit 76543210 0x1e (0x3e) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x/0 x x x x x x x bit 76543210 0x1d (0x3d) eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1c (0x3c) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 22 8197c?avr?05/11 attiny261a/461a/861a old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 5-1 . when eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enab les the eeprom ready interrupt if th e i-bit in sreg is set. writing eerie to zero disables the interrupt. the eep rom ready interrupt generates a constant inter- rupt when non-volatile memory is ready for programming. ? bit 2 ? eempe: eeprom master program enable the eempe bit determines whether writing eepe to o ne will have effect or not. when eempe is set, setting eepe within four cl ock cycles will program the eeprom at the selected address. if eempe is zero, setting eepe will have no effect. when eempe has been written to one by software, hardware clears the bit to zero after four clock cycles. ? bit 1 ? eepe: eeprom program enable the eeprom program enable signal eepe is th e programming enable signal to the eeprom. when eepe is written, the eeprom will be pr ogrammed according to the eepmn bits setting. the eempe bit must be written to one before a logical one is written to eepe, otherwise no eeprom write takes place. when the write a ccess time has elapsed, the eepe bit is cleared by hardware. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal ? eere ? is t he read strobe to the eeprom. when the cor- rect address is set up in the eear register, the eere bit must be written to one to trigger the eeprom read. the eeprom read access takes one instruction, and th e requested data is available immediately. when t he eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. th e user should poll the eepe bit be fore starting the read opera- tion. if a write operation is in progress, it is neither possible to read the eeprom, nor to change the eear register. table 5-1. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 23 8197c?avr?05/11 attiny261a/461a/861a 5.5.5 gpior2 ? general purpose i/o register 2 5.5.6 gpior1 ? general purpose i/o register 1 5.5.7 gpior0 ? general purpose i/o register 0 bit 76543210 0x0c (0x2c) msb lsb gpior2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0b (0x2b) msb lsb gpior1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x0a (0x2a) msb lsb gpior0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 24 8197c?avr?05/11 attiny261a/461a/861a 6. clock system figure 6-1 presents the principal clock systems and t heir distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ?power management and sleep modes? on page 35 . figure 6-1. clock distribution 6.1 clock subsystems the clock subsystems are detailed in the sections below. 6.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general pur pose register file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 6.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counter. the i/o clock is also used by the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. gener a l i/o mod u le s cpu core ram clk i/o avr clock control unit clk cpu fl as h a nd eeprom clk fla s h s o u rce clock w a tchdog timer w a tchdog o s cill a tor re s et logic clock m u ltiplexer w a tchdog clock c a li b r a ted rc o s cill a tor c a li b r a ted rc o s cill a tor adc clk adc cry s t a l o s cill a tor low-fre qu ency cry s t a l o s cill a tor s y s tem clock pre s c a ler pll o s cill a tor clk pck gener a l i/o mod u le s extern a l clock clk pll 25 8197c?avr?05/11 attiny261a/461a/861a 6.1.3 flash clock ? clk flash the flash clock controls operation of the flash in terface. the flash clock is usually active simul- taneously with the cpu clock. 6.1.4 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 6.1.5 fast peripheral clock ? clk pck selected peripherals can be clocked at a frequency higher than the cpu core. the fast periph- eral clock is generated by an on-chip pll circuit. 6.1.6 pll system clock ? clk adc the pll can also be used to generate a system clock. the clock signal can be prescaled to avoid overclocking the cpu. 6.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed and ?0? means programmed. the various choices for each clocking option is given in the following sections. when the cpu wakes up from power-down or power-save, the selected clock source is used to time the start- up, ensuring stable oscillator o peration before instruction exec ution starts. when the cpu starts from reset, there is an additional delay allowi ng the power to reach a stable level before com- table 6-1. device clocking options select (1) vs. pb4 and pb5 functionality device clocking option cksel[3:0] pb4 pb5 external clock (see page 26 ) 0000 xtal1 i/o high-frequency pll clock (see page 26 ) 0001 i/o i/o calibrated internal 8 mhz oscillator (see page 28 ) 0010 i/o i/o internal 128 khz oscillator (see page 29 ) 0011 i/o i/o low-frequency crystal oscillator (see page 29 ) 01xx xtal1 xtal2 crystal oscillator / ceramic resonator 0.4...0.9 mhz (see page 30 ) 1000 1001 xtal1 xtal2 crystal oscillator / ceramic resonator 0.9...3.0 mhz (see page 30 ) 1010 1011 xtal1 xtal2 crystal oscillator / ceramic resonator 3...8 mhz (see page 30 ) 1100 1101 xtal1 xtal2 crystal oscillator / ceramic resonator 8...20 mhz (see page 30 ) 1110 1111 xtal1 xtal2 26 8197c?avr?05/11 attiny261a/461a/861a mencing normal operation. the watchdog oscillator is used for timing this real-time part of the start-up time. the number of wd oscillator cycles used for each time-out is shown in table 6-2 . 6.2.1 external clock to drive the device from an external cloc k source, clki should be driven as shown in figure 6- 2 . to run the device on an ex ternal clock, the cksel fuses must be progra mmed to ?0000?. figure 6-2. external clock drive configuration when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 6-3 . when applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. it is required to en sure that the mcu is kept in reset during such changes in the clock frequency. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency. see ?system clock prescaler? on page 31 for details. 6.2.2 high-frequency pll clock the internal pll generates a clock signal with a frequency eight times higher than the source input. the pll uses the output of the internal 8 mhz oscillator as source and the default setting generates a fast peripheral clock signal of 64 mhz. table 6-2. number of watchdog oscillator cycles typ time-out number of cycles 4 ms 512 64 ms 8k (8,192) table 6-3. start-up times for the external clock selection sut[1:0] start-up time from power- down and power-save additional delay from reset recommended usage 00 6 ck 14ck bod enabled 01 6 ck 14ck + 4 ms fast rising power 10 6 ck 14ck + 64 ms slowly rising power 11 reserved external clock signal clki gnd 27 8197c?avr?05/11 attiny261a/461a/861a the fast peripheral clock, clk pck , can be selected as the clock source for timer/counter1 and a prescaled version of the pll output, clk pll , can be selected as system clock. see figure 6-3 for a detailed illustration on the pll clock system. figure 6-3. pck clocking system the internal pll is enabled when cksel fuse bits are programmed to ?0001?and the plle bit of pllcsr is set. the internal oscillator and the pll are switched off in power down and stand-by sleep modes. when the lsm bit of pllcsr is set, the pll switches from using the output of the internal 8 mhz oscillator to using the output divided by two. the frequency of the fast peripheral clock is effectively divided by two, resulting in a clock frequency of 32 mhz. the lsm bit can not be set if pll clk is used as a system clock. since the pll is locked to the ou tput of the internal 8 mhz oscilla tor, adjusting th e oscillator fre- quency via the osccal register also changes the frequency of the fast peripheral clock. it is possible to adjust the fr equency of the internal oscillator to well above 8 mhz but the fast periph- eral clock will saturate and remain oscillating at about 85 mhz. in this case the pll is no longer locked to the internal oscillator clock signal. ther efore, in order to keep the pll in the correct operating range, it is recommended to program the osccal registers such that the oscillator frequency does not exceed 8 mhz. the plock bit in pllcsr is set when pll is locked. programming cksel fuse bits to ?0001?, the pll output divided by four will be used as a system clock, as shown in table 6-4 . table 6-4. pllck operating modes cksel[3:0] nominal frequency 0001 16 mhz 1/2 8 mhz l s m 8 mhz o s cillator pll 8 x ck s el 3 :0 plle o s ccal 4 mhz 1/4 lock detector pre s caler clkp s3 :0 clk pll plock clk pck o s cillator s xtal1 xtal2 64 / 3 2 mhz 8 mhz 16 mhz 28 8197c?avr?05/11 attiny261a/461a/861a when the pll output is selected as clock source, the start-up times are determined by sut fuse bits as shown in table 6-5 . 6.2.3 calibrated internal 8 mhz oscillator by default, the internal oscilla tor provides an approximately 8 mhz clock signal. though voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 19-2 on page 187 and ?internal oscillato rs? on page 222 for more details. the device is shipped with the ckdiv8 fuse programmed. see ?system clock presca ler? on page 31 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 6-6 . if selected, it will operate with no external comp onents. during rese t, hardware loads the pre-programmed calibration value into the osccal register and thereby automatically cal- ibrates the internal oscillator. the accuracy of this calibration is shown as factory calibration in table 19-2 on page 187 . notes: 1. the device is shipped with this option selected. 2. if the oscillator frequency exceeds the spec ification of the device (depends on v cc ), the ckdiv8 fuse can be programmed to divide the internal frequency by 8. when this oscillator is selected, start- up times are dete rmined by sut fu ses as shown in table 6-7 . note: 1. if the rstdisbl fuse is pr ogrammed, this start-up time will be increased to 14ck + 4 ms to ensure programming mode can be entered. 2. the device is shipped with this option selected. table 6-5. start-up times for the pllck sut[1:0] start-up time from power down additional delay from power-on-reset (v cc = 5.0v) recommended usage 00 14ck + 1k (1024) + 4 ms 4 ms bod enabled 01 14ck + 16k (16384) + 4 ms 4 ms fast rising power 10 14ck + 1k (1024) + 64 ms 4 ms slowly rising power 11 14ck + 16k (16384) + 64 ms 4 ms slowly rising power table 6-6. internal calibrated osc illator operating modes cksel[3:0] nominal frequency 0010 (1) 8.0 mhz (2) table 6-7. start-up times for the internal ca librated oscillator clock selection sut[1:0] start-up time from power-down additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14ck (1) bod enabled 01 6 ck 14ck + 4 ms fast rising power 10 (2) 6 ck 14ck + 64 ms slowly rising power 11 reserved 29 8197c?avr?05/11 attiny261a/461a/861a it is possible to reach a higher accuracy than factory calibration by changing the osccal regis- ter from software. see ?osccal ? oscillator calibrati on register? on page 32 . the accuracy of this calibration is shown as user calibration in table 19-2 on page 187 . when this oscillator is used as device clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed cali- bration value, see section ?calibration byte? on page 170 . 6.2.4 internal 128 khz oscillator the 128 khz internal oscillator is a low power oscillator providing a clock of 128 khz. the fre- quency depends on supply voltage, temperature and batch variations. this clock may be select as the system clock by programmi ng the cksel fuses to ?0011?. when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 6-8 . note: 1. if the rstdisbl fuse is pr ogrammed, this start-up time will be increased to 14ck + 4 ms to ensure programming mode can be entered. 6.2.5 low-frequency crystal oscillator to use a 32.768 khz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting cksel fu ses to ?0100?. the cryst al should be connected as shown in figure 6-4 . to find suitable capacitors please consult the manufacturer?s datasheet. when this oscillator is selected, start-up ti mes are determined by t he sut fuses as shown in table 6-9 . notes: 1. these options should be used only if frequency stability at st art-up is not important. the low-frequency crystal oscillator provides an internal load capacitance, see table 6-10 at each tosc pin. table 6-8. start-up times for the 128 khz internal oscillator sut[1:0] start-up time from power- down and power-save additional delay from reset recommended usage 00 6 ck 14ck (1) bod enabled 01 6 ck 14ck + 4 ms fast rising power 10 6 ck 14ck + 64 ms slowly rising power 11 reserved table 6-9. start-up times for the lo w frequency crystal oscillator clock selection sut[1:0] start-up time from power down additional delay from reset recommended usage 00 1k (1024) ck (1) 4 ms fast rising power or bod enabled 01 1k (1024) ck (1) 64 ms slowly rising power 10 32k (32768) ck 64 ms stable frequency at start-up 11 reserved table 6-10. capacitance of low-frequency crystal oscillator device 32 khz osc. type cap (xtal1/tosc1) cap (xtal2/tosc2) attiny261a/461a/861a system osc. 16 pf 6 pf 30 8197c?avr?05/11 attiny261a/461a/861a 6.2.6 crystal oscillator / ceramic resonator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an on-chip oscillator, as shown in figure 6-4 . either a quartz crystal or a ceramic resonator may be used. figure 6-4. crystal oscillator connections c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 6-11 . for ceramic resonators, the capacitor values given by the manufacturer should be used. notes: 1. this option should not be used with crystals, only with ceramic resonators. the oscillator can operate in three different mo des, each optimized for a specific frequency range. the op erating mode is selected by fuses cksel[3:1] as shown in table 6-11 . the cksel0 fuse together with the sut[1:0] fuses select the start-up times as shown in table 6-12 . table 6-11. crystal oscillator operating modes cksel[3:1] frequency range (mhz) recommended c1 and c2 value (pf) 100 (1) 0.4 - 0.9 ? 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 table 6-12. start-up times for the crysta l oscillator clock selection cksel0 sut[1:0] start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14ck + 4 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14ck + 64 ms ceramic resonator, slowly rising power 0 10 1k (1024) ck (2) 14ck ceramic resonator, bod enabled xtal2 xtal1 gnd c2 c1 31 8197c?avr?05/11 attiny261a/461a/861a notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystal s when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 6.2.7 default clock source the device is shipped with cksel = ?0010?, sut = ?10?, and ckdiv8 programmed. the default clock source setting is therefore the internal oscillator running at 8 mhz with longest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or high-voltage programmer. it should be noted that unprogramming the ckdiv8 fuse may result in overclocking. at low volt- ages the devices are rated for clock frequencies below that of the internal oscillator. see section 19.3 on page 187 for maximum operating frequency versus supply voltage. 6.3 system clock prescaler the system clock can be divided by setting the ?clkpr ? clock prescale register? on page 32 . this feature can be used to decrease power consumption when the requirement for processing power is low. this can be used wit h all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 6-13 on page 33 . 6.3.1 switching time when switching between prescaler settings, the system clock prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu?s clock frequency. hence, it is not possible to determine the state of the prescaler ? even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. 0 11 1k (1024)ck (2) 14ck + 4 ms ceramic resonator, fast rising power 1 00 1k (1024)ck (2) 14ck + 64 ms ceramic resonator, slowly rising power 1 01 16k (16384) ck 14ck crystal oscillator, bod enabled 1 10 16k (16384) ck 14ck + 4 ms crystal oscillator, fast rising power 1 11 16k (16384) ck 14ck + 64 ms crystal oscillator, slowly rising power table 6-12. start-up times for the crystal osc illator clock select ion (continued) cksel0 sut[1:0] start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 32 8197c?avr?05/11 attiny261a/461a/861a from the time the clkps values ar e written, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval, two active clock edges are produced. here, t1 is the previous clock period, and t2 is the perio d corresponding to the new prescaler setting. 6.4 clock output buffer the device can output the system clock on the clko pin (when not used as xtal2 pin). to enable the output, the ckout fuse has to be programmed. this mode is suitable when the chip clock is used to drive other circuits on the syst em. note that the clock will not be output during reset and the normal operation of i/o pin will be overridden when the fuse is programmed. inter- nal rc oscillator, wdt oscillator, pll, and external clock (clki) can be selected when the clock is output on clko. crysta l oscillators (xtal1, xtal2) can not be used for clock output on clko. if the system clock prescaler is used, it is the divided system clock that is output. 6.5 register description 6.5.1 osccal ? oscillato r calibration register ? bits 7:0 ? cal[7:0]: oscillator calibration value the oscillator calibration register is used to tr im the calibrated internal oscillator to remove process variations from the osc illator frequency. a pr e-programmed calibration value is automat- ically written to this register during chip reset, giving the factory calibrated frequency as specified in table 19-2 on page 187 . the application software can write this register to change the oscillator frequency. the os cillator can be calibrated to frequencies as specified in table 19- 2 on page 187 . calibration outside that range is not guaranteed. note that this o scillator is used to time eeprom and flash write accesses , and these write times will be affected accordingly. if the eeprom or flash are writ ten, do not calibrate to more than 8.8 mhz. other wise, the eeprom or flash write may fail. the cal[7:0] bits are used to tu ne the frequency of the oscillator. a setting of 0x00 gives the lowest frequency, and a setting of 0xff gives the highest. 6.5.2 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in clkpr are simultaniosly written to zero. clkpce is cleared by hardware four cycles af ter it is written or when the clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. bit 76543210 0x31 (0x51) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value bit 76543210 0x28 (0x48) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 33 8197c?avr?05/11 attiny261a/461a/861a ? bits 6:4 ? res: reserved bits these bits are reserved and will always read as zero. ? bits 3:0 ? clkps[3:0]: clock prescaler select bits 3 - 0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro- nous peripherals is reduced when a division fact or is used. the division factors are given in table 6-13 . to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired valu e to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of eight at star t up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selcted clock source has a highe r frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. table 6-13. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 34 8197c?avr?05/11 attiny261a/461a/861a 1101 reserved 1110 reserved 1111 reserved table 6-13. clock prescaler select (continued) clkps3 clkps2 clkps1 clkps0 clock division factor 35 8197c?avr?05/11 attiny261a/461a/861a 7. power management and sleep modes the high performance and industry leading code efficiency makes the avr microcontrollers an ideal choise for low power applications. in addition, sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. 7.1 sleep modes figure 6-1 on page 24 presents the different clock systems and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 7-1 shows the different sleep modes and their wake up sources. note: 1. for int0 and int1, only level interrupt. 2. when pll selected as system clock. to enter any of the sleep modes, the se bit in mcucr must be written to logic one and a sleep instruction must be execut ed. the sm[1:0] bits in the mcucr register select which sleep mode (idle, adc noise r eduction, power-down, or standby) will be activated by the sleep instruct ion. see table 7-2 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the st art-up time, executes the interrupt routine, and resumes execution from the instruction followi ng sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the mcu (and for the mcu to enter the interrupt service routine). see ?external interrupts? on page 50 for details. 7.1.1 idle mode when bits sm[1:0] are written to 00, the sleep instructio n makes the mcu enter idle mode, stopping the cpu but allowing analog comparator , adc, timer/counter, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. table 7-1. active clock domains and wake-up sources in different sleep modes sleep mode active clock domains osc. wake-up sources clk cpu clk flash clk io clk adc clk pck clk pll main clock source enabled int0, int1 and pin change spm/eeprom ready interrupt adc interrupt usi interrupt other i/o watchdog interrupt idle xxxx (2) x xxxxxx adc noise reduct. x x (2) xx (1) xxx x power-down x (1) xx standby x (1) xx 36 8197c?avr?05/11 attiny261a/461a/861a idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status register ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. 7.1.2 adc noise reduction mode when the sm[1:0] bits are written to 01, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, and the watchdog to continue operating (if enabled). this sleep mode halts clk i/o , clk cpu , and clk flash , while allowing the ot her clocks to run. this mode improves the noise environment for the adc, enabling higher resolution measure- ments. if the adc is enabled, a conversion starts automatically when this mode is entered. apart form the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, an spm/eeprom ready interrupt, an external level interr upt on int0 or a pin change interrupt can wake up the mcu from adc noise reduction mode. 7.1.3 power-down mode when the sm[1:0] bits are written to 10, the sleep instruction makes the mcu enter power- down mode. in this mode, the os cillator is stopped, while the ex ternal interrupts, and the watch- dog continue operating (if enabled). only an external reset, a watchdog reset, a brown-out reset, an external level interrupt on int0, or a pin change interrupt can wake up the mcu. this sleep mode halts all generated clocks, allowing operation of asynchronous modules, only. 7.1.4 standby mode when the sm[1:0] bits are written to 11 and an external crystal/resonator clock option is selected, the sleep instruction ma kes the mcu enter st andby mode. this m ode is identical to power-down with the exception t hat the oscillator is kept r unning. from sta ndby mode, the device wakes up in six clock cycles. 7.2 software bod disable when the brown-out detector (bod) is enabled by bodlevel fuses (see table 18-4 on page 169 ), the bod is actively monitoring the supply voltage during a sleep period. it is possible to save power by disabling the bod by software in power-down sleep mode. the sleep mode power consumption will then be at the same leve l as when bod is glo bally disabled by fuses. if bod is disabled by software, the bod function is turned off immediately after entering the sleep mode. upon wake-up from sleep, bod is automatically enabled again. this ensures safe operation in case the v cc level has dropped during the sleep period. when the bod has been disabled, the wake-up time from sleep mode will be approximately 60s to ensure that the bod is working corr ectly before the mcu continues executing code. bod disable is controlled by the bods (bod sleep) bit of bod control register, see ?mcucr ? mcu control register? on page 38 . writing this bit to one turns off bod in power-down and stand-by, while writing a zero keeps the bod active . the default setting is zero, i.e. bod active. writing to the bods bit is controlled by a timed sequence and an enable bit, see ?mcucr ? mcu control register? on page 38 . 37 8197c?avr?05/11 attiny261a/461a/861a 7.3 power reduction register the power reduction register (prr), see ?prr ? power reduction register? on page 39 , pro- vides a method to stop the clock to individual per ipherals to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled be fore stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. in all other sleep modes, the clock is already stopped. see ?supply current of i/o modules? on page 197 for examples. in all other sleep modes, the clock is already stopped. 7.4 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 7.4.1 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparat or should be disabled. in the other sleep modes, the analog comparator is automatically di sabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be dis- abled in all sleep modes. ot herwise, the internal volt age reference will be enabled, independent of sleep mode. refer to ?ac ? analog comparator? on page 136 for details on how to configure the analog comparator. 7.4.2 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?adc ? analog to digital converter? on page 141 for details on adc operation. 7.4.3 brown-out detector if the brown-out detector is not needed in the application, this module should be turned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to ?brown-out detection? on page 42 for details on how to configure the brown-out detector. 7.4.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage refe rence will be disabled and it w ill not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 43 for details on the start-up time. 38 8197c?avr?05/11 attiny261a/461a/861a 7.4.5 watchdog timer if the watchdog timer is not needed in the application, this module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?watchdog timer? on page 43 for details on how to configure the watchdog timer. 7.4.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important thing is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensu res that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 58 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or has an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr0, didr1). refer to ?didr0 ? digital input disable register 0? on page 160 or ?didr1 ? digital input dis- able register 1? on page 160 for details. 7.5 register description 7.5.1 mcucr ? mcu control register the mcu control register contains control bits for power management. ? bit 7 ? bods: bod sleep in order to disable bod during sleep the bods bit must be written to logic one. this is controlled by a timed sequence and the enable bit, bodse. first, both bods and bodse must be set to one. second, within four clock cycles, bods must be set to one and bodse must be set to zero. the bods bit is active thre e clock cycles after it is set. a sleep instruction must be exe- cuted while bods is active in order to turn off the bod for the actual sleep mode. the bods bit is automatically cleared after three clock cycles. ? bit 5 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu enteri ng the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. bit 76543210 0x35 (0x55) bods pud se sm1 sm0 bodse isc01 isc00 mcucr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 39 8197c?avr?05/11 attiny261a/461a/861a ? bits 4:3 ? sm[1:0]: sleep mode select bits 1 and 0 these bits select between the four available sleep modes as shown in table 7-2 . ? bit 2 ? bodse: bod sleep enable the bodse bit enables setting of bods control bit, as explained on bods bit description. bod disable is controlled by a timed sequence. 7.5.2 prr ? power reduction register the power reduction register provides a met hod to reduce power consumption by allowing peripheral clock signals to be disabled. ? bits 7:4 ? res: reserved bits these bits are reserved and will always read zero. ? bit 3 ? prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabled, operation will cont inue like before the shutdown. ? bit 2 ? prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, operation will cont inue like before the shutdown. ? bit 1 ? prusi: power reduction usi writing a logic one to this bit shuts down t he usi by stopping the clock to the module. when waking up the usi again, the usi should be re initialized to ensure proper operation. ? bit 0 ? pradc: power reduction adc writing a logic one to this bit shuts down the adc. the adc must be disabled before shut down. also analog comparator needs this clock. table 7-2. sleep mode select sm1 sm0 sleep mode 00idle 0 1 adc noise reduction 1 0 power-down 1 1 standby bit 76543 2 10 0x36 (0x56) ? ? ? ? prtim1 prtim0 prusi pradc prr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 40 8197c?avr?05/11 attiny261a/461a/861a 8. system control and reset 8.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in figure 8-1 shows the reset logic. electrical parameters of the reset circuitry are given in table 19-4 on page 188 . figure 8-1. reset logic the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 25 . mcu status register (mcusr) brown-out reset circuit reset circuit watchdog timer bodlevel [2:0] delay counters cksel[1:0] ck timeout s q r wdrf borf extrf porf data bus clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit vcc reset internal reset counter reset 41 8197c?avr?05/11 attiny261a/461a/861a 8.2 reset sources the attiny261a/461a/861a has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. 8.2.1 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in ?system and reset characteristics? on page 188 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a fa ilure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is acti vated again, without any delay, when v cc decreases below the detection level. figure 8-2. mcu start-up, reset tied to v cc figure 8-3. mcu start-up, reset extended externally v reset time-out internal reset t tout v pot v rst cc reset time-out internal reset t tout v pot v rst v cc 42 8197c?avr?05/11 attiny261a/461a/861a 8.2.2 external reset an external reset is generated by a low level on the reset pin if enabled. reset pulses longer than the minimum pulse width (see ?system and reset characteristics? on page 188 ) will gener- ate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 8-4. external reset during operation 8.2.3 brown-out detection a brown-out detection (bod) circuit monitors the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 8-5 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 8-5 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for lon- ger than t bod given in ?system and reset characteristics? on page 188 . figure 8-5. brown-out reset during operation cc v cc reset time-out internal reset v bot- v bot+ t tout 43 8197c?avr?05/11 attiny261a/461a/861a 8.2.4 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to ?watchdog timer? on page 43 for details on operation of the watchdog timer. figure 8-6. watchdog reset during operation 8.3 internal voltage reference attiny261a/461a/861a features an internal bandgap reference. this reference is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. the bandgap voltage varies with supply voltage and temperature, as can be seen in figure 20-45 on page 221 . 8.3.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in ?system and reset characteristics? on page 188 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel[2:0] fuse bits). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. 8.4 watchdog timer the watchdog timer is clocked fr om an on-chip oscillator, which runs at 128 khz. by controlling the watchdog timer prescaler, the watchdog reset interval can be adjusted as shown in table 8-3 on page 48 . the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a device reset occurs. ten different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the device resets and executes from the reset vector. for timing details on the watchdog reset, refer to table 8-3 on page 48 . ck cc 44 8197c?avr?05/11 attiny261a/461a/861a the wathdog timer can also be configured to generate an interrupt instead of a reset. this can be very helpful when using the watchdog to wake-up from power-down. to prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse wdton as shown in table 8-1 refer to ?timed sequences for changing the configuration of the watchdog timer? on page 44 for details. figure 8-7. watchdog timer 8.4.1 timed sequences for changing the configuration of the watchdog timer the sequence for changing configuration differs slightly between the two safety levels. separate procedures are described for each level. 8.4.1.1 safety level 1 in this mode, the watchdog time r is initially disabled, but can be enabled by writing the wde bit to one without any restriction. a timed sequence is needed when disabling an enabled watch- dog timer. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be writ- ten to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, in the same operation, write the wde and wdp bits as desired, but with the wdce bit cleared. 8.4.1.2 safety level 2 in this mode, the watchdog time r is always enabled, and the wde bit will always read as one. a timed sequence is needed when changing the watchdog time-out period. to change the watchdog time-out, the following procedure must be followed: table 8-1. wdt configuration as a function of the fuse settings of wdton wdton safety level wdt initial state how to disable the wdt how to change time- out unprogrammed 1 disabled timed sequence no limitations programmed 2 enabled always enabled timed sequence osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k mcu reset watchdog prescaler 128 khz oscillator watchdog reset wdp0 wdp1 wdp2 wdp3 wde 45 8197c?avr?05/11 attiny261a/461a/861a 1. in the same operation, write a logical one to wdce and wde. even though the wde always is set, the wde must be written to one to start the timed sequence. 2. within the next four clock cycles, in the same operation, write the wdp bits as desired, but with the wdce bit cleared. the value written to the wde bit is irrelevant. 8.4.2 code examples the following code example shows one assembly and one c function for turning off the wdt. the example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. note: see ?code examples? on page 6 . assembly code example wdt_off: wdr ; clear wdrf in mcusr ldi r16, (0< 47 8197c?avr?05/11 attiny261a/461a/861a the next time-out will generate a reset. to avoid the watchdog reset, wdie must be set after each interrupt. ? bit 4 ? wdce: watchdog change enable this bit must be set when the wde bit is writte n to logic zero. otherwis e, the watchdog will not be disabled. once written to one, hardware will clear this bit after four clock cycles. refer to the description of the wde bit for a watchdog disable procedure. this bit must also be set when changing the prescaler bits. see ?timed sequences for changing the configuration of the watchdog timer? on page 44. ? bit 3 ? wde: watchdog enable when the wde is written to logic one, the watchdog timer is enabled, and if the wde is written to logic zero, the watchdog timer function is di sabled. wde can only be cleared if the wdce bit has logic level one. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be writ- ten to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logic 0 to wde. this disables the watchdog. in safety level 2, it is not possible to disable the watchdog timer, even with the algorithm described above. see ?timed sequences for changing the configuration of the watchdog timer? on page 44. in safety level 1, wde is overridden by wdrf in mcusr. see ?mcusr ? mcu status regis- ter? on page 46 for description of wdrf. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared before disabling the watchdog with the procedure described above. this feature ensures multiple re sets during conditions causing failure, and a safe start-up after the failure. note: if the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. if the watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. to avoi d this situation, the app lication software should always clear the wdrf flag and the wde control bit in the initialization routine. table 8-2. watchdog timer configuration wde wdie watchdog timer state action on time-out 0 0 stopped none 0 1 running interrupt 1 0 running reset 1 1 running interrupt 48 8197c?avr?05/11 attiny261a/461a/861a ? bits 5, 2:0 ? wdp[3:0]: watchdog timer prescaler 3 - 0 the wdp[3:0] bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding timeout periods are shown in table 8-3 . notes: 1. if selected, one of the valid settings below 0b1010 will be used. table 8-3. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16 ms 0 0 0 1 4k (4096) cycles 32 ms 0 0 1 0 8k (8192) cycles 64 ms 0 0 1 1 16k (16384) cycles 0.125 s 0 1 0 0 32k (32764) cycles 0.25 s 0 1 0 1 64k (65536) cycles 0.5 s 0 1 1 0 128k (131072) cycles 1.0 s 0 1 1 1 256k (262144) cycles 2.0 s 1 0 0 0 512k (524288) cycles 4.0 s 1 0 0 1 1024k (1048576) cycles 8.0 s 1010 reserved (1) 1011 1100 1101 1110 1111 49 8197c?avr?05/11 attiny261a/461a/861a 9. interrupts this section describes the specifics of the interrupt handling as performed in attiny261a/461a/861a. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 12 . 9.1 interrupt vectors interrupt vectors of attiny261a/461a/861a are described in table 9-1 below. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the most typical and general program setup for the reset and interrupt vector addresses in attiny261a/461a/861a is shown in the following program example. table 9-1. reset and interrupt vectors vector no. program address source interrupt definition 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset 2 0x0001 int0 external interrupt request 0 3 0x0002 pcint pin change interrupt request 4 0x0003 timer1_compa timer/counter1 compare match a 5 0x0004 timer1_compb timer/counter1 compare match b 6 0x0005 timer1_ovf timer/counter1 overflow 7 0x0006 timer0_ovf timer/counter0 overflow 8 0x0007 usi_start usi start 9 0x0008 usi_ovf usi overflow 10 0x0009 ee_rdy eeprom ready 11 0x000a ana_comp analog comparator 12 0x000b adc adc conversion complete 13 0x000c wdt watchdog time-out 14 0x000d int1 external interrupt request 1 15 0x000e timer0_compa timer/counter0 compare match a 16 0x000f timer0_compb timer/counter0 compare match b 17 0x0010 timer0_capt timer/counter1 capture event 18 0x0011 timer1_compd timer/counter1 compare match d 19 0x0012 fault_protection timer/counter1 fault protection 50 8197c?avr?05/11 attiny261a/461a/861a address labels code comments 0x0000 rjmp reset ; reset handler 0x0001 rjmp ext_int0 ; irq0 handler 0x0002 rjmp pcint ; pcint handler 0x0003 rjmp tim1_compa ; timer1 comparea handler 0x0004 rjmp tim1_compb ; timer1 compareb handler 0x0005 rjmp tim1_ovf ; timer1 overflow handler 0x0006 rjmp tim0_ovf ; timer0 overflow handler 0x0007 rjmp usi_start ; usi start handler 0x0008 rjmp usi_ovf ; usi overflow handler 0x0009 rjmp ee_rdy ; eeprom ready handler 0x000a rjmp ana_comp ; analog comparator handler 0x000b rjmp adc_isr ; adc conversion handler 0x000c rjmp wdt ; wdt interrupt handler 0x000d rjmp ext_int1 ; irq1 handler 0x000e rjmp tim0_compa ; timer0 comparea handler 0x000f rjmp tim0_compb ; timer0 compareb handler 0x0010 rjmp tim0_capt ; timer0 capture event handler 0x0011 rjmp tim1_compd ; timer1 compared handler 0x0012 rjmp fault_protection ; timer1 fault protection 0x0013 reset: ldi r16, low(ramend) ; main program start 0x0014 ldi r17, high(ramend); tiny861 have also sph 0x0015 out spl, r16 ; set stack pointer to top of ram 0x0016 out sph, r17 ; tiny861 have also sph 0x0017 sei ; enable interrupts 0x0018 51 8197c?avr?05/11 attiny261a/461a/861a 9.2.1 low level interrupt a low level interrupt on int0 is detected asyn chronously. this means that the interrupt source can be used for waking the part also from sleep modes other than idle (the i/o clock is halted in all sleep modes except idle). note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. the start- up time is defined by the su t and cksel fuses as described in ?clock system? on page 24 . if the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service ro utine but continue from the instruction fol- lowing the sleep command. 9.3 register description 9.3.1 mcucr ? mcu control register the mcu register contains control bits for interrupt sense control. ? bits 1:0 ? isc0[1:0]: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the extern al pin int0 or int1 if the sreg i-flag and the corresponding interrupt mask are set. the level and edges on the external int0 or int1 pin that activate the interrupt are defined in table 9-2 . the value on the int0 or int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pulses are not guaranteed to generate an inter- rupt. if low level interrupt is se lected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. 9.3.2 gimsk ? general interrupt mask register ? bit 7 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu bit 76543210 0x35 (0x55) bods pud se sm1 sm0 bodse isc01 isc00 mcucr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 9-2. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 or int1 generates an interrupt request. 0 1 any logical change on int0 or int1 generates an interrupt request. 1 0 the falling edge of int0 or int1 generates an interrupt request. 1 1 the rising edge of int0 or int1 generates an interrupt request. bit 76543210 0x3b (0x5b) int1int0pcie1pcie0????gimsk read/writer/wr/wr/wr/wrrrr initial value00000000 52 8197c?avr?05/11 attiny261a/461a/861a control register (mcucr) define whether the external interrupt is activated on rising and/or fall- ing edge of the int1 pin or level sensed. activi ty on the pin will cause an interrupt request even if int1 is configured as an output. the corresponding interrupt of external interrupt request 1 is executed from the int1 interrupt vector. ? bit 6 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the exter- nal pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu control register (mcucr) define whether the external interrupt is activated on rising and/or fall- ing edge of the int0 pin or level sensed. activi ty on the pin will cause an interrupt request even if int0 is configured as an output. the corresponding interrupt of external interrupt request 0 is executed from the int0 interrupt vector. ? bit 5 ? pcie1: pin change interrupt enable when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt is enabled. any change on any enabled pcint[7:0] or pcint[15:12] pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci interrupt vector. pcint[7:0] and pc int[15:12] pins are enabled individually by the pcmsk0 and pcmsk1 register. ? bit 4 ? pcie0: pin change interrupt enable when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt is enabled. any change on any enabled pcint[11:8] pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci interrupt vector. pcint[11:8] pins are enabled individually by the pcmsk1 register. ? bits 3:0 ? res: reserved bits these bits are reserved and will always read as zero. 9.3.3 gifr ? general interrupt flag register ? bit 7 ? intf1: external interrupt flag 1 when an edge or logic change on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in gimsk are set (o ne), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int1 is configured as a level interrupt. ? bit 6 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (o ne), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. bit 76543210 0x3a (0x5a) int1 intf0 pcif ? ? ? ? ? gifr read/writer/wr/wr/wrrrrr initial value00000000 53 8197c?avr?05/11 attiny261a/461a/861a ? bit 5 ? pcif: pin change interrupt flag when a logic change on any pcint15 pin triggers an interrupt request, pcif becomes set (one). if the i-bit in sreg and the pcie bit in gimsk are set (one), the mcu will jump to the cor- responding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bits 4:0 ? res: reserved bits these bits are reserved and will always read as zero. 9.3.4 pcmsk0 ? pin change mask register a ? bits 7:0 ? pcint[7:0]: pin change enable mask 7:0 each pcint[7:0] bit selects whether pin c hange interrupt is enabled on the corresponding i/o pin. if pcint[7:0] is set and the pcie1 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint[7:0] is cleared, pin change interrupt on the corresponding i/o pin is disabled. 9.3.5 pcmsk1 ? pin change mask register b ? bits 7:0 ? pcint[15:8]: pin change enable mask 15:8 each pcint[15:8] bit selects whether pin c hange interrupt is enabled on the corresponding i/o pin. if pcint[11:8] is set and the pcie0 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin, and if pcint[15:12] is set and the pcie1 bit in gimsk is set, pin change interrupt is enabled on the corresponding i/o pin . if pcint[15:8] is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 0x23 (0x43) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11001000 bit 76543210 0x22 (0x42) pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 54 8197c?avr?05/11 attiny261a/461a/861a 10. i/o ports all avr ports have true read-modi fy-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin driver is stro ng enough to drive led displays directly. all port pins have indi- vidually selectable pull-up resistors with a suppl y-voltage invariant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 10-1 . see ?electrical character- istics? on page 185 for a complete list of parameters. figure 10-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a progr am, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o regis- ters and bit locations are listed in ?register description? on page 68 . three i/o memory address locations are allocated for each port, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bit in the pinx register, will result in a toggle in the correspond- ing bit in the data register. in addition, the pu ll-up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set. using the i/o port as general digital i/o is described in ?ports as general digital i/o? on page 55 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 59 . refer to the individual module sectio ns for a full description of the alter- nate functions. note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu see figure "general digital i/o" for details pxn 55 8197c?avr?05/11 attiny261a/461a/861a 10.1 ports as gener al digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 10-2 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 10-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are co mmon to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 10.1.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description? on page 68 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is c onfigured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 56 8197c?avr?05/11 attiny261a/461a/861a be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 10.1.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 10.1.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. norma lly, the pull-up enabled state is fully accept- able, as a high-impedant enviro nment will not notice the differenc e between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b10) as an intermediate step. table 10-1 summarizes the control signals for the pin value. 10.1.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 10-2 , the pinxn register bit and the preceding latch con- stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 10-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 10-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 57 8197c?avr?05/11 attiny261a/461a/861a figure 10-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd,max and tpd,min, a single signal tr ansition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 10-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is one system clock period. figure 10-4. synchronization when reading a software assigned pin value xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 58 8197c?avr?05/11 attiny261a/461a/861a 10.1.5 digital input enable and sleep modes as shown in figure 10-2 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denot ed sleep in the figure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pins. sl eep is also overri dden by various other alternate functions as described in ?alternate port functions? on page 59 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.1.6 unconnected pins if some pins are unused, it is recommended to ens ure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (reset, active mode and idle mode). the simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. in this case, the pull-up will be disabled during reset. if low po wer consumption during reset is important, it is recommended to use an external pull-up or pulldown. connecting unused pins directly to v cc or gnd is not recommended, since this ma y cause excessive curr ents if the pin is accidentally configured as an output. 10.1.7 program examples the following code examples show how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. assembly code example ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 61 8197c?avr?05/11 attiny261a/461a/861a table 10-2 summarizes the function of the overriding signals. the pin and port indexes from fig- ure 10-5 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 10-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital in put is enabled/disabled when dieov is set/cleared, regardl ess of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 62 8197c?avr?05/11 attiny261a/461a/861a 10.2.1 alternate functions of port a the port a pins with alternate function are shown in table 10-3 . ? port a, bit 7 ? adc6/ain0/pcint7 ? adc6: analog to digital converter, channel 6 . ? ain0: analog comparator input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. ? pcint7: pin change interrupt source 8. ? port a, bit 6 ? adc5/ain1/pcint6 ? adc5: analog to digital converter, channel 5. ? ain1: analog comparator input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. ? pcint6: pin change interrupt source 6. table 10-3. port b pins alternate functions port pin alternate function pa 7 adc6: adc input channel 6 ain0: analog comparator input pcint7: pin change interrupt 0, source 7 pa 6 adc5: adc input channel 5 ain1: analog comparator input pcint6: pin change interrupt 0, source 6 pa 5 adc4: adc input channel 4 ain2: analog comparator input pcint5: pin change interrupt 0, source 5 pa 4 adc3: adc input channel 3 icp0: timer/counter0 input capture pin pcint4: pin change interrupt 0, source 4 pa 3 aref: external analog reference pcint3: pin change interrupt 0, source 3 pa 2 adc2: adc input channel 2 int1: external interrupt 1 input usck: usi clock (three wire mode) scl : usi clock (two wire mode) pcint2: pin change interrupt 0, source 2 pa 1 adc1: adc input channel 1 do: usi data output (three wire mode) pcint1:pin change interrupt 0, source 1 pa 0 adc0: adc input channel 0 di: usi data input (three wire mode) sda: usi data input (two wire mode) pcint0: pin change interrupt 0, source 0 63 8197c?avr?05/11 attiny261a/461a/861a ? port a, bit 5 ? adc4/ain2/pcint5 ? adc4: analog to digital converter, channel 4. ? ain2: analog comparator input. configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. ? pcint5: pin change interrupt source 5. ? port a, bit 4 ? adc3/icp0/pcint4 ? adc3: analog to digital converter, channel 3. ? icp0: timer/counter0 input capture pin. ? pcint4: pin change interrupt source 4. ? port a, bit 3 ? aref/pcint3 ? aref: external analog reference for adc. pullup and output driver are disabled on pa3 when the pin is used as an external reference or internal voltage reference with external capacitor at the aref pin. ? pcint3: pin change interrupt source 3. ? port a, bit 2 ? adc2/int1/usck/scl/pcint2 ? adc2: analog to digital converter, channel 2. ? int1: the pa2 pin can serve as an external interrupt source 1. ? usck: three-wire mode univer sal serial interface clock. ? scl: two-wire mode serial clock for usi two-wire mode. ? pcint2: pin change interrupt source 2. ? port a, bit 1 ? adc1/do/pcint1 ? adc1: analog to digital converter, channel 1. ? do: three-wire mode universal serial interface data output. three-wire mode data output overrides porta1 value and it is driven to the port when data direction bit dda1 is set. porta1 still enables the pull-up, if the direction is input and porta1 is set. ? pcint1: pin change interrupt source 1. ? port a, bit 0 ? adc0/di/sda/pcint0 ? adc0: analog to digital converter, channel 0. ? di: data input in usi three-wire mode. usi th ree-wire mode does not override normal port functions, so pin must be configure as an input for di function. ? sda: two-wire mode serial interface data. ? pcint0: pin change interrupt source 0. 64 8197c?avr?05/11 attiny261a/461a/861a table 10-4 and table 10-5 relate the alternate functions of port a to the overriding signals shown in figure 10-5 on page 60 . table 10-4. overriding signals for alternate functions in pa[7:4] signal name pa7/adc6/ain0/ pcint7 pa6/adc5/ain1/ pcint6 pa5/adc4/ain2/ pcint5 pa4/adc3/icp0/ pcint4 puoe0000 puov0000 ddoe0000 ddov0000 pvoe0000 pvov0000 ptoe0000 dieoe pcint7 ? pcie + adc6d pcint6 ? pcie + adc5d pcint5 ? pcie + adc4d pcint4 ? pcie + adc3d dieov adc6d adc5d adc4d adc3d di pcint7 pcint6 pcint5 icp0/pcint4 aio adc6, ain0 adc5, ain1 adc4, ain2 adc3 table 10-5. overriding signals for alternate functions in pa[3:0] signal name pa3/aref/ pcint3 pa2/adc2/int1/ usck/scl/pcint2 pa1/adc1/do/ pcint1 pa0/adc0/di/sda/ pcint0 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 usi_two_wire ? usipos 0 usi_two_wire ? usipos ddov 0 (usi_scl_hold + portb2 ) ? ddb2 ? usipos 0 (sda + portb0 ) ? ddrb0 ? usipos pvoe 0 usi_two_wire ? ddrb2 usi_three_wi re ? usipos usi_two_wire ? ddrb0 ? usipos pvov 0 0 do ? usipos 0 ptoe 0 usi_ptoe ? usipos 0 0 dieoe pcint3 ? pcie pcint2 ? pcie + int1 + adc2d + usisie ? usipos pcint1 ? pcie + adc1d pcint0 ? pcie + adc0d + usisie ? usipos dieov 0 adc2d adc1d adc0d di pcint3 usck/scl/int1/ pcint2 pcint1 di/sda/pcint0 aio aref adc2 adc1 adc0 65 8197c?avr?05/11 attiny261a/461a/861a 10.2.2 alternate functions of port b the port b pins with alternate function are shown in table 10-6 . ? port b, bit 7 ? reset /dw/adc10/pcint15 ? reset, reset pin: when the rstdisbl fuse is programmed, this pin functions as a normal i/o pin, and the part will have to rely on po wer-on reset and brown-out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. ? if pb7 is used as a reset pin, ddb 7, portb7 and pinb7 will all read 0. ? dw: when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the reset port pi n is configured as a wire-a nd (open-drain) bi-directional i/o pin with pull-up enabled and becomes the communication gateway between target and emulator. table 10-6. port b pins alternate functions port pin alternate function pb7 reset : reset pin dw: debugwire i/o adc10: adc input channel 10 pcint15:pin change interrupt 0, source 15 pb6 adc9: adc input channel 9 t0: timer/counter0 clock source int0: external interrupt 0 input pcint14:pin change interrupt 0, source 14 pb5 xtal2: crystal oscillator output clko: system clock output oc1d: timer/counter1 compare match d output adc8: adc input channel 8 pcint13:pin change interrupt 0, source 13 pb4 xtal1: crystal oscillator input clki: external clock input oc1d : inverted timer/counter1 compare match d output adc7: adc input channel 7 pcint12:pin change interrupt 0, source 12 pb3 oc1b: timer/counter1 compare match b output pcint11:pin change interrupt 0, source 11 pb2 usck: usi clock (three wire mode) scl : usi clock (two wire mode) oc1b : inverted timer/counter1 compare match b output pcint10:pin change interrupt 0, source 10 pb1 do: usi data output (three wire mode) oc1a: timer/counter1 compare match a output pcint9: pin change interrupt 1, source 9 pb0 di: usi data input (three wire mode) sda: usi data input (two wire mode) oc1a : inverted timer/counter1 compare match a output pcint8: pin change interrupt 1, source 8 66 8197c?avr?05/11 attiny261a/461a/861a ? adc10: adc input channel 10. note that adc input channel 10 uses analog power. ? pcint15: pin change interrupt source 15. ? port b, bit 6 ? adc9/t0/int0/pcint14 ? adc9: adc input channel 9. note that adc input channel 9 uses analog power. ? t0: timer/counter0 counter source. ? int0: the pb6 pin can serve as an external interrupt source 0. ? pcint14: pin change interrupt source 14. ? port b, bit 5 ? xtal2/clko/adc8/pcint13 ? xtal2: chip clock oscillator pin 2. used as cl ock pin for crystal oscillator or low-frequency crystal oscillator. when used as a clock pi n, the pin can not be used as an i/o pin. ? clko: the divided system clock can be output on the pb5 pin, if the ckout fuse is programmed, regardless of the portb5 and ddb5 settings. it will also be output during reset. ? oc1d output compare match output: the pb5 pin can serve as an external output for the timer/counter1 compare match d when configured as an output (dda1 set). the oc1d pin is also the output pin for the pwm mode timer function. ? adc8: adc input channel 8. note that adc input channel 8 uses analog power. ? pcint13: pin change interrupt source 13. ? port b, bit 4 ? xtal1/ clki/oc1b/adc7/pcint12 ? xtal1/clki: chip clock oscillator pin 1. used for all chip clock sources except internal calibrated oscillator. when used as a clock pi n, the pin can not be used as an i/o pin. ?oc1d : inverted output compare match output: the pb4 pin can serve as an external output for the timer/counter1 compare match d when configured as an output (dda0 set). the oc1d pin is also the inverted output pin for the pwm mode timer function. ? adc7: adc input channel 7. note that adc input channel 7 uses analog power. ? pcint12: pin change interrupt source 12. ? port b, bit 3 ? oc1b/pcint11 ? oc1b, output compare match output: the pb3 pin can serve as an external output for the timer/counter1 compare match b. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. ? pcint11: pin change interrupt source 11. ? port b, bit 2 ? sck/usck/scl/oc1b /pcint10 ? usck: three-wire mode univer sal serial interface clock. ? scl: two-wire mode serial clock for usi two-wire mode. ?oc1b : inverted output compare match output: the pb2 pin can serve as an external output for the timer/counter1 compare match b when configured as an output (ddb2 set). the oc1b pin is also the inverted output pin for the pwm mode timer function. ? pcint10: pin change interrupt source 10. 67 8197c?avr?05/11 attiny261a/461a/861a ? port b, bit 1 ? miso/do/oc1a/pcint9 ? do: three-wire mode universal serial interface data output. three-wire mode data output overrides portb1 value and it is driven to the port when data direction bit ddb1 is set (one). portb1 still enables the pull-up, if the dire ction is input and po rtb1 is set (one). ? oc1a: output compare match output: the pb1 pin can serve as an external output for the timer/counter1 compare match b when configured as an output (ddb1 set). the oc1a pin is also the output pin for the pwm mode timer function. ? pcint9: pin change interrupt source 9. ? port b, bit 0 ? mosi/di/sda/oc1a /pcint8 ? di: data input in usi three-wire mode. usi th ree-wire mode does not override normal port functions, so pin must be configure as an input for di function. ? sda: two-wire mode serial interface data. ?oc1a : inverted output compare match output: the pb0 pin can serve as an external output for the timer/counter1 compare match b when configured as an output (ddb0 set). the oc1a pin is also the inverted output pin for the pwm mode timer function. ? pcint8: pin change interrupt source 8. table 10-7 and table 10-8 relate the alternate functions of port b to the overriding signals shown in figure 10-5 on page 60 . note: 1. ?1? when the fuse is ?0? (programmed). table 10-7. overriding signals for alternate functions in pb[7:4] signal name pb7/reset/ dw/adc10/ pcint15 pb6/adc9/t0/ int0/pcint14 pb5/xtal2/clko/ oc1d/adc8/ pcint13 (1) pb4/xtal1/ oc1d /adc7/ pcint12 (1) puoe rstdisbl (1) ? dwen (1) 0 intrc ? extclk intrc puov1000 ddoe rstdisbl (1) ? dwen (1) 0 intrc ? extclk intrc ddov debugwire transmit 0 0 0 pvoe 0 0 oc1d enable oc1d enable pvov 0 0 oc1d oc1d ptoe0000 dieoe 0 rstdisbl + (pcint14 ? pcie + adc9d) intrc ? extclk + pcint13 ? pcie + adc8d intrc + pcint12 ? pcie + adc7d dieov adc10d adc9d (intrc ? extclk) + adc8d intrc ? adc7d di pcint15 t0/int0/pcint14 pcint13 pcint12 aio reset / adc10 adc9 xtal2, adc8 xtal1, adc7 68 8197c?avr?05/11 attiny261a/461a/861a note: 1. intrc means that one of th e internal oscillators is sele cted (by the cksel fuses), extck means that external clock is selected (by the cksel fuses). 10.3 register description 10.3.1 mcucr ? mcu control register ? bit 6 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 55 for more details about this feature. 10.3.2 porta ? port a data register 10.3.3 ddra ? port a data direction register table 10-8. overriding signals for alternate functions in pb[3:0] signal name pb3/oc1b/ pcint11 pb2/sck/usck/scl/o c1b /pcint10 pb1/miso/do/oc1a/ pcint9 pb0/mosi/di/sda/ oc1a /pcint8 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 usi_two_wire ? usipos 0 usi_two_wire ? usipos ddov 0 (usi_scl_hold + portb2 ) ? ddb2 ? usipos 0 (sda + portb0 ) ? ddb0 ? usipos pvoe oc1b enable oc1b enable + usipos ? usi_two_wire ? ddb2 oc1a enable + usipos ? usi_three_wire oc1a enable + (usi_two_wire ? ddb0 ? usipos ) pvov oc1b oc1b oc1a + (do ? usipos ) oc1a ptoe 0 usitc ? usipos 00 dieoe pcint11 ? pcie pcint10 ? pcie + usisie ? usipos pcint9 ? pcie pcint8 ? pcie + (usisie ? usipos ) dieov 0 0 0 0 di pcint11 usck/scl/pcint10 pcint9 di/sda/pcint8 aio bit 7 6 5 4 3 2 1 0 0x35 (0x55) bods pud se sm1 sm0 bodse isc01 isc00 mcucr read/write r/w r/w r/w r/w r/w r/w r r initial value 0 0 0 0 0 0 0 0 bit 76543210 0x1b (0x3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1a (0x3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 69 8197c?avr?05/11 attiny261a/461a/861a 10.3.4 pina ? port a input pins address 10.3.5 portb ? port b data register 10.3.6 ddrb ? port b data direction register 10.3.7 pinb ? port b input pins address bit 76543210 0x19 (0x39) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x18 (0x38) portb7 portb6 portb5 portb4 port b3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x17 (0x37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x16 (0x36) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a 70 8197c?avr?05/11 attiny261a/461a/861a 11. timer/counter0 11.1 features ? clear timer on compare match (auto reload) ? one input capture unit ? four independent interrupt sources (tov0, ocf0a, ocf0b, icf0) ? 8-bit mode with two indepe ndent output compare units ? 16-bit mode with one independent output compare unit 11.2 overview timer/counter0 is a general purpose 8/16-bit timer/counter module, with two/one output com- pare units and input capture feature. the general operation of timer/counter0 is described in 8/16-bit mode. a simplified block dia- gram of the 8/16-bit timer/counter is shown in figure 11-1 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bol d. for actual placement of i/o pins, refer to ?pin- out attiny261a/461a/861a? on page 2 . device-specific i/o register and bit locations are listed in the ?register description? on page 83 . figure 11-1. 8-/16-bit timer/counter block diagram 11.2.1 registers the timer/counter0 low byte register (tcnt0l) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated int.req. in figure 11-1 ) signals are all clock select timer/counter data b u s ocrnb = tcntnl noise canceler icpn = edge detector control logic top count clear direction tovn (int. req.) ocna (int. req.) ocnb (int. req.) icfn (int. req.) tccrna tccrnb ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn = ocrna tcntnh fixed top value 71 8197c?avr?05/11 attiny261a/461a/861a visible in the timer interrupt flag register (tifr). all interrupts are individually masked with the timer interrupt mask register (timsk). tifr and timsk are not shown in the figure. in 16-bit mode one more 8-bit register is av ailable, the timer/counter0 high byte register (tcnt0h). also, in 16-bit mode, there is only one output compare unit as the two output com- pare registers, ocr0a and ocr0b, are combined to one, 16-bit output compare register, where ocr0a contains the low byte and ocr0b contains the high byte of the word. when accessing 16-bit registers, spec ial procedures described in section ?accessing registers in 16- bit mode? on page 79 must be followed. 11.2.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a or compare unit b. howe ver, when using the register or bit defines in a program, the precise form must be used, i.e. tcnt0l for accessing timer/counter0 counter value, and so on. the definitions in table 11-1 are also used extensively throughout the document. 11.3 clock sources the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic is controlled by the clock select (cs0[2:0]) bits located in the timer/counter control register 0 b (tccr0b), and controls which clock source and edge the timer/counter uses to increment its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). 11.3.1 prescaler the timer/counter can be clocked directly by the system clock (by setting the csn[2:0] = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. see figure 11-2 for an illustration of the prescaler unit. table 11-1. definitions constant description bottom the counter reaches bottom when it becomes 0x00 max the counter reaches its maximum when it becomes 0xff (decimal 255) top the counter reaches the top when it become s equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assi gnment depends on the mode of operation 72 8197c?avr?05/11 attiny261a/461a/861a figure 11-2. prescaler for timer/counter0 note: 1. the synchronization logic on the input pins ( t0) is shown in figure 11-3 . the prescaled clock has a frequency of f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. see table 11-4 on page 84 for details. 11.3.1.1 prescaler reset the prescaler is free running, i.e. it operates independently of the clock select logic of the timer/counter. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler will have implicati ons for situations w here a prescaled clock is used. one exam- ple of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn[2:0] > 1). the number of system clock cycl es from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execution. 11.3.2 external clock source an external clock source applied to the t0 pin can be used as timer/counter clock (clk t0 ). the t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchro- nized (sampled) signal is then passed through the edge detector. figure 11-3 shows a functional equivalent block diagram of the t0 synchronizati on and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t 0 pulse for each positive (csn[2:0] = 7) or negative (csn[2:0] = 6) edge it detects. see table 11-4 on page 84 for details. psr0 clear clk t0 t0 clk i/o synchronization 73 8197c?avr?05/11 attiny261a/461a/861a figure 11-3. t0 pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t0 has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. 11.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 11-4 shows a block diagram of the counter and its surroundings. table 11-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. the counter is incremented at each timer clock (clk t0 ) until it passes its top value and then restarts from bottom. the counting sequence is determined by the setting of the ctc0 bit located in the timer/counter control register (tccr0a). for more details about counting sequences, see ?modes of operation? on page 76 . clk t0 can be generated from an external or tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn 74 8197c?avr?05/11 attiny261a/461a/861a internal clock source, selected by the clock sele ct bits (cs0[2:0]). wh en no clock source is selected (cs0[2:0] = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the timer/counter overflow flag (tov0) is set when the counter reaches the maximum value and it can be used for generating a cpu interrupt. 11.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icp0 pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 11-4 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. figure 11-4. input capture unit block diagram the output compare register ocr0a is a dual-purpose register that is also used as an 8-bit input capture register icr0. in 16-bit input capture mode the output compare register ocr0b serves as the high byte of the input capture register icr0. in 8-bit input capture mode the output compare register ocr0b is free to be used as a normal output compare register, but in 16-bit input capture mode the output compare unit cannot be used as there are no free output compare register(s). even though the input capture register is called icr0 in this sec- tion, it is refering to the output compare register(s). when a change of the logic level (an event) occurs on the input capture pin (icp0), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a c apture is triggered, the value of the counter (tcnt0) is written to the input capture register (icr0). the input capture flag (icf0) is set at icf0 (int.req.) analog comparator write icr0 (16-bit register) ocr0b (8-bit) noise canceler icp0 edge detector temp (8-bit) data bus (8-bit) ocr0a (8-bit) tcnt0 (16-bit counter) tcnt0h (8-bit) tcnt0l (8-bit) acic0* icnc0 ices0 aco* 75 8197c?avr?05/11 attiny261a/461a/861a the same system clock as the tcnt0 value is copied into input capture register. if enabled (ticie0 = 1), the input capture flag generates an input capture interrupt. the icf0 flag is auto- matically cleared when the interrupt is execut ed. alternatively the icf0 flag can be cleared by software by writing a logical one to its i/o bit location. 11.5.1 input capture trigger source the default trigger source for the input capture unit is the input capture pin (icp0). timer/counter0 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture enable (acic0) bit in the timer/counter control register a (tccr0a). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp0) and the analog comparator output (aco) inputs are sampled using the same technique as for the t0 pin ( figure 11-4 on page 84 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. an input capture can also be triggered by software by controlling the port of the icp0 pin. 11.5.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc0) bit in timer/counter control register b (tccr0b). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icr0 register. the noise canceler uses the syst em clock and is therefore not affected by the prescaler. 11.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icr0 register before the nex t event occurs, the icr0 will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture interrupt, the icr0 register should be read as early in the inter- rupt handler routine as possible. the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr0 register has been read. after a change of the edge, the input capture flag (icf0) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the trigger edge change is not required (if an interrupt handler is used). 11.6 output compare unit the comparator continuously compares timer/counter (tcnt0) with the output compare reg- isters (ocr0a and ocr0b), and whenever the timer/counter equals to the output compare regisers, the comparator signals a match. a match will set t he output compare flag at the next timer clock cycle. in 8-bit mode the match can set either the output compare flag ocf0a or 76 8197c?avr?05/11 attiny261a/461a/861a ocf0b, but in 16-bit mode the match can set only the output compare flag ocf0a as there is only one output compare unit. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be cleared by software by writing a log- ical one to its i/o bit location. figure 11-5 shows a block diagram of the output compare unit. figure 11-5. output compare unit, block diagram 11.6.1 compare match bloc king by tcnt0 write all cpu write operations to the tcnt0h/l regi ster will block any compar e match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0a/b to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 11.6.2 using the output compare unit since writing tcnt0h/l will block all compare matc hes for one timer clock cycle, there are risks involved when changing tcnt0h/l when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0h/l equals the ocr0a/b value, the compare match will be missed. 11.7 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the timer/counter width (tcw0), input capture enable (icen0) and wave genera- tion mode (ctc0) bits. see ?tccr0a ? timer/counter0 control register a? on page 83 . table 11-3 summarises the different modes of operation. 11.7.1 normal, 8-bit mode in normal 8-bit mode (see table 11-3 ), the counter (tcnt0l) is incrementing until it overruns when it passes its maximum 8-bit value (max = 0xff) and then restarts from the bottom (0x00). ocfn x (int.req.) = (8/16-bit comparator ) ocrnx data b u s tcntn table 11-3. modes of operation mode icen0 tcw0 ctc0 mode of operation top update of ocrx at tov flag set on 0000normal, 8-bit mode 0xff immediatemax (0xff) 1001ctc mode, 8-bit ocr0a immediatemax (0xff) 2 0 1 x normal, 16-bit mode 0x ffff immediate max (0xffff) 3 1 0 x input capture mode, 8-bit 0xff immediate max (0xff) 4 1 1 x input capture mode, 16-bit 0xffff immediate max (0xffff) 77 8197c?avr?05/11 attiny261a/461a/861a the overflow flag (tov0) is set in the same timer clock cycle as when tcnt0l becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. how- ever, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. th ere are no special cases to consider in the normal 8-bit mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. 11.7.2 clear timer on compare match (ctc) 8-bit mode in clear timer on compare or ctc mode, see table 11-3 on page 76 , the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output fre- quency. it also simplifies the operati on of counting external events. the timing diagram for the ctc mode is shown in figure 11-6 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 11-6. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 11.7.3 normal, 16-bit mode in 16-bit mode, see table 11-3 on page 76 , the counter (tcnt0h/l) is a incrementing until it overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). the over flow flag (tov0) will be set in the same timer clock cycle as the tcnt0h/l becomes zero. the tov0 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. tcntn ocnx interrupt flag set 1 4 period 2 3 78 8197c?avr?05/11 attiny261a/461a/861a 11.7.4 8-bit input capture mode the timer/counter0 can also be used in an 8-bit input capture mode, see table 11-3 on page 76 for bit settings. for full description, see the section ?input capture unit? on page 74 . 11.7.5 16-bit input capture mode the timer/counter0 can also be used in a 16-bit input capture mode, see table 11-3 on page 76 for bit settings. for full description, see the section ?input capture unit? on page 74 . 11.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 11-7 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value. figure 11-7. timer/counter timing diagram, no prescaling figure 11-8 shows the same timing data, but with the prescaler enabled. figure 11-8. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 11-9 on page 79 shows the setting of ocf0a and ocf0b in normal mode. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 79 8197c?avr?05/11 attiny261a/461a/861a figure 11-9. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 11-10 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode. figure 11-10. timer/counter timing diagram, ctc mode, with prescaler (f clk_i/o /8) 11.9 accessing register s in 16-bit mode in 16-bit mode (the tcw0 bit is set to one) the tcnt0h/l and ocr0a/b or tcnt0l/h and ocr0b/a are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. the 16-bit timer/counter has a single 8-bit register for te mporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both cop- ied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. there is one exception in the temporary register usage. in the output compare mode the 16-bit output compare register ocr0a/b is read without the temporary register, because the output compare register contains a fixed value that is only changed by cpu access. however, in 16- bit input capture mode the icr0 register formed by the ocr0a and ocr0b registers must be accessed with the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk pck clk tn (clk pck /8) 80 8197c?avr?05/11 attiny261a/461a/861a the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr0a/b registers. note: see ?code examples? on page 6 . the assembly code example returns the tcnt0h/l value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code example ... ; set tcnt 0 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 0 h,r17 out tcnt 0 l,r16 ; read tcnt 0 into r17:r16 in r16,tcnt 0 l in r17,tcnt 0 h ... c code example unsigned int i; ... /* set tcnt0 to 0x01ff */ tcnt0h = 0x01; tcnt0l = 0xff; /* read tcnt0 into i */ i = tcnt0l; i |= ((unsigned int)tcnt0h << 8); ... 81 8197c?avr?05/11 attiny261a/461a/861a the following code examples sh ow how to do an atomic read of the tcnt0 register contents. reading any of the ocr0 register can be done by using the same principle. note: see ?code examples? on page 6 . the assembly code example returns the tcnt0h/l value in the r17:r16 register pair. assembly code example tim0_readtcnt 0 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 0 into r17:r16 in r16,tcnt 0 l in r17,tcnt 0 h ; restore global interrupt flag out sreg,r18 ret c code example unsigned int tim0_readtcnt0( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt0 into i */ i = tcnt0l; i |= ((unsigned int)tcnt0h << 8); /* restore global interrupt flag */ sreg = sreg; return i; } 82 8197c?avr?05/11 attiny261a/461a/861a the following code examples show how to do an atomic write of the tcnt0h/l register con- tents. writing any of the ocr0a/b registers can be done by using the same principle. note: see ?code examples? on page 6 . the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt0h/l. 11.9.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example tim0_writetcnt 0 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 0 to r17:r16 out tcnt 0 h,r17 out tcnt 0 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example void tim0_writetcnt0( unsigned int i ) { unsigned char sreg; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt0 to i */ tcnt0h = (i >> 8); tcnt0l = ( unsigned char )i; /* restore global interrupt flag */ sreg = sreg; } 83 8197c?avr?05/11 attiny261a/461a/861a 11.10 register description 11.10.1 tccr0a ? timer/counter0 control register a ? bit 7 ? tcw0: timer/counter0 width when this bit is written to one 16- bit mode is selected as described figure 11-7 on page 78 . timer/counter0 width is set to 16-bits and the output compare registers ocr0a and ocr0b are combined to form one 16-bit output com pare register. because the 16-bit registers tcnt0h/l and ocr0b/a are accessed by the av r cpu via the 8-bit data bus, special proce- dures must be followed. these procedures are described in section ?accessing registers in 16- bit mode? on page 79 . ? bit 6 ? icen0: input capture mode enable when this bit is written to onem, the input capture mode is enabled. ? bit 5 ? icnc0: input capture noise canceler setting this bit activates the input capture nois e canceler. when the noise canceler is acti- vated, the input from the input capture pin (icp0) is filtered. the filter function requires four successive equal valued samples of the icp0 pin for changing its output. the input capture is therefore delayed by four system clock cycles when the noise canceler is enabled. ? bit 4 ? ices0: input capture edge select this bit selects which edge on the input capture pin (icp0) that is used to trigger a capture event. when the ices0 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices0 bit is written to one, a rising (positive) edge will trigger the capture. when a cap- ture is triggered according to the ices0 setting, the counter value is copied into the input capture register. the event will al so set the input capt ure flag (icf0), and this can be used to cause an input capture interrupt, if this interrupt is enabled. ? bit 3 ? acic0: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter0 to be trig- gered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the compar ator utilize the noise canceler and edge select features of the timer/counter0 input capture interrupt. when written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter0 input capture interrupt, the ticie0 bit in the timer interrupt mask register (timsk) must be set. ? bits 2:1 ? res: reserved bits these bits are reserved and will always read zero. ? bit 0 ? ctc0: waveform generation mode this bit controls the counting sequence of the counter, the source for maximum (top) counter value, see figure 11-7 on page 78 . modes of operation supported by the timer/counter unit are: normal mode (counter) and clear timer on compare match (ctc) mode (see ?modes of oper- ation? on page 76 ). bit 76543210 0x15 (0x35) tcw0 icen0 icnc0 ices0 acic0 ? ? ctc0 tccr0a read/write r/w r/w r/w r/w r/w r r r/w initial value00000000 84 8197c?avr?05/11 attiny261a/461a/861a 11.10.2 tccr0b ? timer/counter0 control register b ? bit 4 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psr0 bit is kept, hence keeping the prescaler reset signal asserted. this ensures that the timer/counter is halted and can be configured without the risk of advanc- ing during configuration. when the tsm bit is written to zero, the psr0 bit is cleared by hardware, and the timer/counter start counting. ? bit 3 ? psr0: prescaler reset timer/counter0 when this bit is one, the timer/counter0 prescale r will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. ? bits 2:0 ? cs0[2:0]: clock select0, bits 2 - 0 the clock select0 bits 2, 1, and 0 define the prescaling source of timer0. if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 11.10.3 tcnt0l ? timer/counter0 register low byte the timer/counter0 register low byte, tcnt0l, gives direct access, both for read and write operations, to the timer/ counter unit 8-bit counter. writing to the tcnt0l register blocks (dis- ables) the compare match on the following time r clock. modifying th e counter (tcnt0l) while the counter is running, introduces a risk of missing a compare match between tcnt0l and the ocr0x registers. in 16-bit mode the tcnt0l register contains the lower part of the 16-bit timer/counter0 register. bit 76543210 0x33 (0x53) ? ? ? tsm psr0 cs02 cs01 cs01 tccr0b read/write r r r r/w r/w r/w r/w r/w initial value00000000 table 11-4. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x32 (0x52) tcnt0l[7:0] tcnt0l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 85 8197c?avr?05/11 attiny261a/461a/861a 11.10.4 tcnt0h ? timer/count er0 register high byte when 16-bit mode is selected (the tcw0 bit is set to one) the timer/counter register tcnt0h combined to the timer/counter register tcnt0l gives direct access, both for read and write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is per- formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing registers in 16-bit mode? on page 79 11.10.5 ocr0a ? timer/counter0 output compare register a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt0l). a match can be used to generate an output compare interrupt. in 16-bit mode the ocr0a register contains the low byte of the 16-bit output compare register. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is performed usi ng an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing registers in 16-bit mode? on page 79 . 11.10.6 ocr0b ? timer/counter0 output compare register b the output compare register b contains an 8-bi t value that is continuously compared with the counter value (tcnt0l in 8-bit mode and tcnth in 16-bit mode). a match can be used to gen- erate an output compare interrupt. in 16-bit mode the ocr0b register contains the high byte of the 16-bit output compare regis- ter. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is perf ormed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing reg- isters in 16-bit mode? on page 79 . 11.10.7 timsk ? timer/counter0 interrupt mask register ? bit 4 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and th e i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed bit 76543210 0x14 (0x34) tcnt0h[7:0] tcnt0h read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x13 (0x33) ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x12 (0x32) ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x39 (0x59) ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 timsk read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 86 8197c?avr?05/11 attiny261a/461a/861a if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 3 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enab led. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. ? bit 0 ? ticie0: timer/counter0, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 49. ) is executed when the icf0 flag, located in tifr, is set. 11.10.8 tifr ? timer/counter0 interrupt flag register ? bit 4 ? ocf0a: output compare flag 0 a the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the cor- responding interrupt handling vector. alternativel y, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. the ocf0a is also set in 16-bit mode when a compare match occurs between the timer/coun- ter and 16-bit data in ocr0b/a. the ocf0a is not set in input capture mode when the output compare register ocr0a is used as an input capture register. ? bit 3 ? ocf0b: output compare flag 0 b the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when executing the cor- responding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. the ocf0b is not set in 16-bit output compare mode when the output compare register ocr0b is used as the high byte of the 16-bit output compare register or in 16-bit input cap- ture mode when the output compare register ocr0b is used as the hi gh byte of the input capture register. bit 76543210 0x38 (0x58) ocf1d ocf1a ocf1b ocf0a ocf0b tov1 tov0 icf0 tifr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 87 8197c?avr?05/11 attiny261a/461a/861a ? bit 1 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. ? bits 0 ? icf0: timer/counter0, input capture flag this flag is set when a capture event occurs on the icp0 pin. when the input capture register (icr0) is set to be used as the top value, the icf0 flag is set when the counter reaches the top value. icf0 is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icf0 can be cleared by writing a logic one to its bit location. 88 8197c?avr?05/11 attiny261a/461a/861a 12. timer/counter1 12.1 features ? 8/10-bit accuracy ? three independent output compare units ? clear timer on compare match (auto reload) ? glitch free, phase and frequency co rrect pulse width modulator (pwm) ? variable pwm period ? high speed asynchronous and synchron ous clocking with dedicated prescaler ? independent dead time generators for each pwm channel ? fault protection unit ca n disable pwm output pins ? five independent interrupt sources (tov1, ocf1a, ocd1b, ocf1d, fpf1) 12.2 overview timer/counter1 is a general purpose high speed timer/counter module, with three independent output compare units, and with pwm support. the timer/counter1 features a high resolution and a high accuracy usage with the lower pres- caling opportunities. it can also support three accurate and high speed pulse width modulators using clock speeds up to 64 mhz. in pwm mode timer/counter1 and the output compare regis- ters serve as triple stand-alone pwms with non-overlapping non-inverted and inverted outputs. similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. a simplified block diagram of the timer/counter1 is shown in figure 12-1 . figure 12-1. timer/counter1 block diagram 8-bit databus t/c int. flag register (tifr) 10-bit comparator 8-bit output compare register a (ocr1a) t/c int. mask register (timsk) timer/counter1 (tcnt1) direction timer/counter1 control logic ocf1b tov1 toie1 ocie1b ocie1a ocf1a tov1 ocf1b oc1a ocf1a t/c control register a (tccr1a) com1b1 pwm1a pwm1b com1b0 foc1a foc1b 10-bit comparator 8-bit output compare register b (ocr1b) com1a1 com1a0 t/c control register b (tccr1b) cs12 psr1 cs11 cs10 cs13 oc1a oc1b oc1b dead time generator dead time generator 10-bit comparator 8-bit output compare register c (ocr1c) 10-bit comparator 8-bit output compare register d (ocr1d) com1a1 pwm1d com1a0 foc1d t/c control register c (tccr1c) ocf1d ocf1d ocie1d oc1d oc1d dead time generator psr1 psr1 ocw1a ocw1b ocw1d 2-bit high byte register (tc1h) w gm11 fpen1 t/c control register d (tccr1e) com1b1 com1b0 com1d1 com1d0 fpnc1 fpes1 fpac1 10-bit output compare register b 10-bit output compare register c 10-bit output compare register d 10-bit output compare register a clear count clk t/c control register c (tccr1d) fault_protection w gm10 fpie1 fpf1 oc1oe5 oc1oe4 oc1oe3 oc1oe2 oc1oe1 oc1oe0 fpie1 fpf1 89 8197c?avr?05/11 attiny261a/461a/861a for actual placement of the i/o pins, refer to ?pinout attiny261a/461a/861a? on page 2 . the device-specific i/o register and bit locations are listed in the ?register description? on page 111 . 12.2.1 speed the maximum speed of the timer/counter1 is 64 mhz. however, if a supply voltage below 2.7 volts is used, it is recommended to use the low speed mode (lsm), because the timer/counter1 is not running fast enough on low voltage levels. in the low speed mode the fast peripheral clock is scaled down to 32 mhz. for more details about the low speed mode, see ?pllcsr ? pll control and status register? on page 119 . 12.2.2 accuracy the timer/counter1 is a 10-bit timer/counter modu le that can alternatively be used as an 8-bit timer/counter. the timer/counter1 registers are bas ically 8-bit registers, but on top of that there is a 2-bit high byte register (tc1h) that can be used as a common temporary buffer to access the two msbs of the 10-bit timer/counte r1 registers by the avr cpu via the 8-bit data bus, if the 10-bit accuracy is used. whereas, if the two msbs of the 10-bit registers are written to zero the timer/counter1 is working as an 8-bit timer/counter. when reading the low byte of any 8-bit register the two msbs are written to the tc1h register, and when writing the low byte of any 8-bit register the two msbs are written from the tc1h register. special procedures must be followed when accessing the 10-bit timer/counte r1 values via the 8-bi t data bus. these proce- dures are described in the section ?accessing 10-bit registers? on page 107 . 12.2.3 registers the timer/counter (tcnt1) and output compare registers (ocr1a, ocr1b, ocr1c and ocr1d) are 8-bit registers that are used as a data source to be compared with the tcnt1 con- tents. the ocr1a, ocr1b and ocr1d registers determine the action on the oc1a, oc1b and oc1d pins and they can also generate the co mpare match interrupts. the ocr1c holds the timer/counter top value, i.e. the clear on compare match value. t he timer/counter1 high byte register (tc1h) is a 2-bit register that is used as a comm on temporary buffer to access the msb bits of the timer/counter1 regist ers, if the 10-bit accuracy is used. interrupt request (overflow tov1, and compare matches ocf1a, ocf1b, ocf1d and fault pro- tection fpf1) signals are visible in the timer in terrupt flag register (tifr) and timer/counter1 control register d (tccr1d). the interrupts are individually masked with the timer interrupt mask register (timsk) and the fpie1 bit in the timer/counter1 control register d (tccr1d). control signals are found in the timer/counter control regi sters tccr1a, tccr1b, tccr1c, tccr1d and tccr1e. 12.2.4 synchronization in asynchronous clocking mode the timer/counter1 and the prescaler allow running the cpu from any clock source while the prescaler is opera ting on the fast peripheral clock (pck) having frequency of 64 mhz (or 32 mhz in low speed mode). this is possible because there is a syn- chronization boundary between the cpu clock domain and the fast peripheral clock domain. figure 12-2 shows timer/counter 1 synchronization register block diagram and describes syn- chronization delays in between registers. note that all clock gating details are not shown in the figure. the timer/counter1 register values go through the internal synchronization registers, which cause the input synchronization delay, before af fecting the counter operation. the registers tccr1a, tccr1b, tccr1c, tccr1d, ocr1a, ocr1b, ocr1c and ocr1d can be read 90 8197c?avr?05/11 attiny261a/461a/861a back right after writing the register. the read back values are delayed for the timer/counter1 (tcnt1) register, timer/counter1 high byte register (tc1h) and flags (ocf1a, ocf1b, ocf1d and tov1), because of the input and output synchronization. the system clock frequency must be lower than half of the pc k frequency, because the syn- chronization mechanism of the asynchronous time r/counter1 needs at least two edges of the pck when the system clock is high . if the frequency of th e system clock is too high, it is a risk that data or control values are lost. figure 12-2. timer/counter1 synchronization register block diagram. 12.2.5 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a, b, c or d. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 8-bit databus ocr1a ocr1a_si tcnt1_so ocr1b ocr1b_si ocr1c ocr1c_si tccr1a tccr1a_si tccr1b tccr1b_si tcnt1 tcnt1_si ocf1a ocf1a_si ocf1b ocf1b_si tov1 tov1_si tov1_so ocf1b_so ocf1a_so tcnt1 s a s a pcke ck pck io-registers input synchronization registers timer/counter1 output synchronization registers sync mode async mode 1 ck delay 1/2 ck delay ~1/2 ck delay 1 pck delay 1 pck delay ~1 ck delay tcnt1 ocf1a ocf1b tov1 1/2 ck delay 1 ck delay ocr1d ocr1d_si tc1h tc1h_si tccr1c tccr1c_si tccr1d ocf1d ocf1d_si ocf1d_so ocf1d tc1h_so tc1h tccr1d_si 91 8197c?avr?05/11 attiny261a/461a/861a counter value and so on. the definitions in table 12-1 are used extensively throughout the document. 12.3 clock sources the timer/counter is clocked internally, either from ck or pck. see bits csxx in table 12-17 on page 115 and bit pcke in ?pllcsr ? pll control and status register? on page 119 . 12.3.1 prescaler figure 12-3 shows the timer/counter1 prescaler that supports two clocking modes, a synchro- nous clocking mode and an asynchronous clocking mode. the synchronous clocking mode uses the system clock (ck) as a clock timebase and asynchronous mode uses the fast peripheral clock (pck) as a clock time bas e. the pcke bit from the pllc sr register enables the asyn- chronous mode when it is set (?1?). figure 12-3. timer/counter1 prescaler in the asynchronous clocking mode the clock se lections are from pck to pck/16384 and stop, and in the synchronous clocking mode the clock selections are from ck to ck/16384 and stop. the clock options are illustrated in figure 12-3 and desribed in ?tccr1b ? timer/counter1 control register b? on page 114 . the frequency of the fast peripheral clock is 64 mhz or 32 mhz in low speed mode (the lsm bit in pllcsr register is set to one). the low speed mode is recommended to use when the sup- ply voltage below 2.7 volts are used. table 12-1. definitions constant description bottom the counter reaches bottom when it becomes 0x00 max the counter reaches its maximum when it becomes 0xff (decimal 255) top the counter reaches the top when it become s equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assi gnment depends on the mode of operation timer/counter1 count enable psr1 cs10 cs11 cs12 pck 64/32 mhz 0 cs13 14-bit t/c prescaler t1ck/2 t1ck t1ck/4 t1ck/8 t1ck/16 t1ck/32 t1ck/64 t1ck/128 t1ck/256 t1ck/512 t1ck/1024 t1ck/2048 t1ck/4096 t1ck/8192 t1ck/16384 s a ck pcke t1ck 92 8197c?avr?05/11 attiny261a/461a/861a 12.3.1.1 prescaler reset setting the psr1 bit in tccr1b register resets the prescaler. it is possible to use the prescaler reset for synchronizing the timer/counter to program execution. 12.3.1.2 prescaler initializ ation for asynchronous mode to change timer/counter1 to the asynchronous mode follow the procedure below: 1. enable pll. 2. wait 100 s for pll to stabilize. 3. poll the plock bit until it is set. 4. set the pcke bit in the pllcsr regist er which enables the asynchronous mode. 12.4 counter unit the main part of the timer/counter1 is the programmable bi-directional counter unit. figure 12- 4 shows a block diagram of the counter and its surroundings. figure 12-4. counter unit block diagram signal description (internal signals): count tcnt1 increment or decrement enable. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t n timer/counter clock, referred to as clk t1 in the following. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has re ached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t1 ). the timer clock is generated from an synchronous system clock or an asynchronous pll clock using the clock select bits (cs1[3:0]) and the pck enable bit (pcke). when no clock source is selected (cs1[3:0] = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, regardless of whether clk t1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence of the timer/counter1 is determined by bits wgm1[1:0], pwm1a and pwm1b, located in the timer/counter1 cont rol registers (tccr1a, tccr1c and tccr1d). for more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 98 . the timer/counter overflow flag (tov1) is set according to the mode of operation and can be used for generating a cpu interrupt. data b u s tcnt1 control logic count tov1 top timer/counter1 count enable ( from prescaler ) bottom direction clear pck ck pcke clk t1 93 8197c?avr?05/11 attiny261a/461a/861a 12.4.1 counter initialization for asynchronous mode to set timer/counter1 to asynchronous mode follow the procedure below: 1. enable pll. 2. wait 100 s for pll to stabilize. 3. poll the plock bit until it is set. 4. set the pcke bit in the pllcsr register which enables the asynchronous mode. 12.5 output compare unit the comparator continuously compares tcnt1 with the output compare registers (ocr1a, ocr1b, ocr1c and ocr1d). whenever tcnt1 equals to the output compare register, the comparator signals a match. a match will set the output compare flag (ocf1a, ocf1b or ocf1d) at the next timer clock cycle. if the corresponding interrupt is enabled, the output com- pare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternativel y, the flag can be cleared by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by bits pwm1a, pwm1b, wgm1[1:0] and com1x[1:0]. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 98. ). figure 12-5 shows a block diagram of the output compare unit. figure 12-5. output compare unit, block diagram the ocr1x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal mode of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr1x compare registers to either top or bottom of the counting sequence. the synchronization pr events the occurrence of odd-length, non-sym- ocfn x (int .req.) = (10-bit comparator ) 8-bit data bus tcntn wgm10 wav ef o r m gen er at o r comnx[1:0] pwm nx tcnh ocwnx 10-bit tcntn 10-bit ocrnx ocrnx focn top bot tom 94 8197c?avr?05/11 attiny261a/461a/861a metrical pwm pulses, thereby making the output glitch-free. see figure 12-6 for an example. during the time between the write and the update operation, a read from ocr1a, ocr1b, ocr1c or ocr1d will read the contents of the temporary location. this means that the most recently written value always will read out of ocr1a, ocr1b, ocr1c or ocr1d. figure 12-6. effects of unsynchronized ocr latching 12.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (foc1x) bit. forcin g compare match will not set the ocf1x flag or reload/cle ar the timer, but the wa veform output (ocw1x) will be updated as if a real compare match had occurred (the com1x[1:0] bits settings define whether the waveform output (ocw1x) is set, cleared or toggled). 12.5.2 compare match bloc king by tcnt1 write all cpu write operations to the tcnt1 register will block any compare ma tch that occur in the next timer clock cycle, even when the timer is st opped. this feature allows ocr1x to be initial- ized to the same value as tcnt1 without triggering an interrupt when the timer/counter clock is enabled. 12.5.3 using the output compare unit since writing tcnt1 in any mode of operatio n will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt1 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt1 value equal to bottom when the counter is down-counting. the setup of the waveform output (ocw1x) should be performed before setting the data direc- tion register for the port pin to output. the easiest way of setting the ocw1x value is to use the force output compare (foc1x) strobe bits in normal mode. the oc1x keeps its value even when changing between waveform generation modes. be aware that the com1x[1:0] bits are not double buffered together with the compare value. changing the com1x[1:0] bits will take effect immediately. output compare waveform ocwnx output compare wafeform ocwnx unsynchronized wfnx latch synchronized wfnx latch counter value compare value counter value compare value compare value changes glitch compare value changes 95 8197c?avr?05/11 attiny261a/461a/861a 12.6 dead time generator the dead time generator is provided for the timer/counter1 pwm output pairs to allow driving external power control switches safely. the dead time generator is a separate block that can be used to insert dead times (non-overlapping times) for the timer/counter1 complementary output pairs oc1x and oc1x when the pwm mode is enabled and the com1x[1:0] bits are set to ?01?. see figure 12-7 below. figure 12-7. block diagram of waveform generator and dead time generator. the tasks are shared as follows: the waveform generator generates the output (ocw1x) and the dead time generator generates the non-overlapping pwm output pair from the output. three dead time generators are provided, one for each pwm output. the non-overlap time is adjustable and the pwm output and it?s complementary output are adjusted separately, and independently for both pwm outputs. the dead time generation is based on 4-bit down counters that count the dead time, as shown in figure 12-8 . figure 12-8. dead time generator there is a dedicated prescaler in front of the dead time generator that can divide the timer/counter1 clock (pck or ck) by 1, 2, 4 or 8. this provides for large range of dead times that can be generated. the prescaler is controlled by two control bits dtps1[1:0]. the block has also a rising and falling edge detector that is used to start the dead time counting period. depending on the edge, one of the transitions on the rising edges, oc1x or oc1x is delayed until the counter has counted to zero. the comparator is used to compare the counter with zero and stop the dead time insertion when zero has been reached. the counter is loaded with a 4-bit dt1h or dt1l value from dt1 i/o register, depending on the edge of the waveform output (ocw1x) when the dead time insertion is started. the output compare output are delayed by one timer clock cycle at minimum from the waveform output when the dead time is adjusted to ocnx pin wgm10 waveform generator top focn comnx bottom pwmnx ocwnx dead time generator ocnx pin dtnh dtnl dtpsn ck or pck clock ocnx ocnx clock control ocnx ocnx ck or pck clock ocwnx 4-bit counter comparator dtnl dtnh dead time pre-scaler dtpsn dtn i/o register data bus (8-bit) tccrnb register pwm1x pwm1x 96 8197c?avr?05/11 attiny261a/461a/861a zero. the outputs oc1x and oc1x are inverted, if the pwm inversion mode bit pwm1x is set. this will also cause both outputs to be high during the dead time. the length of the counting period is user adjustable by selecting the dead time prescaler setting by using the dtps1[1:0] control bits, and selecting then the dead time value in i/o register dt1. the dt1 register consists of tw o 4-bit fields, dt1h and dt1l that control the dead time periods of the pwm output and its' complementary output separately in terms of the number of pres- caled dead time ge nerator clock cycles. thus the rising edge of oc1x and oc1x can have different dead time periods as the t non-overlap / rising edge is adjusted by the 4-bit dt1h value and the t non-overlap / falling edge is adjusted by the 4-bit dt1l value. figure 12-9. the complementary output pair, com1x[1:0] = 1 12.7 compare match output unit the compare output mode (com1x[1:0]) bits have two functions. the waveform generator uses the com1x[1:0] bits for defining the inverted or non-inverted waveform output (ocw1x) at the next compare match. also, the com1x[1:0] bits control the oc1x and oc1x pin output source. figure 12-10 on page 97 shows a simplified schematic of the logic affected by the com1x[1:0] bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x[1:0] bits are shown. in normal mode (non-pwm) the dead time genera tor is disabled and it is working like a syn- chronizer: the output compare (oc1x) is delayed from the waveform output (ocw1x) by one timer clock cycle. whereas in fast pwm mode and in phase and frequency correct pwm mode when the com1x[1:0] bits are set to ?01? both the non-inverted and the inverted output compare output are generated, and an user programmable dead time delay is inserted for these complementary output pairs (oc1x and oc1x ). the functionality in pwm modes is similar to normal mode when any other com1x[1:0] bit setup is used. when referring to the oc1x state, the reference is for the output compare output (oc1x) from the dead time generator, not the oc1x pin. if a system reset occur, the oc1x is reset to ?0?. ocnx (comnx = 1) t non-overlap / rising edge t non-overlap / falling edge ocnx ocwnx 97 8197c?avr?05/11 attiny261a/461a/861a figure 12-10. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc1x / oc1x ) from the dead time generator if either of the com1x[1:0] bits are set. however, the oc1x pin direction (input or output) is still controlled by the data di rection register (ddr) fo r the port pin. the data direction register bit for the oc1x and oc1x pins (ddr_oc1x and ddr_oc1x) must be set as output before the oc1x and oc1x values are visible on the pin. the port override function is independent of the output compare mode. data bus portb0 ddrb0 dq ddrb1 portb1 dq dq dq clk i/o portb2 ddrb2 d q ddrb3 portb3 d q d q d q portb4 ddrb4 dq ddrb5 portb5 dq dq dq 1 0 1 0 oc1d pin 2 1 0 dead time generator d q q ocw1d clk tn oc1d pin output compare pin configuration com1d[1:0] wgm11 oc1oe[5:4] 1 0 1 0 1 0 oc1b pin 2 1 0 dead time generator b q q ocw1b clk tn oc1b pin output compare pin configuration com1b[1:0] wgm11 oc1oe[3:2] 1 0 1 0 oc1a pin 0 1 dead time generator a q q ocw1a clk tn oc1a pin output compare pin configuration com1a[1:0] wgm11 oc1oe[1:0] 1 0 oc1a oc1a oc1b oc1b oc1d oc1d 98 8197c?avr?05/11 attiny261a/461a/861a the design of the output compare pin configuration logic allows initialization of the oc1x state before the output is enabled. note that some com1x[1:0] bit settings are reserved for certain modes of operation. for output compare pin configurations refer to table 12-2 on page 99 , table 12-3 on page 101 , table 12-4 on page 103 , table 12-5 on page 104 , table 12-6 on page 104 , and table 12-7 on page 105 . 12.7.1 compare output mode and waveform generation the waveform generator uses the com1x[1:0] bits differently in normal mode and pwm modes. for all modes, setting the com1x[1:0] = 0 tells the waveform generator that no action on the ocw1x output is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 12-8 on page 111 . for fast pwm mode, refer to table 12-9 on page 111 , and for the phase and frequency correct pwm refer to table 12-10 on page 112 . a change of the com1x[1:0] bits state will have effect at the first compare match after the bits are written. for non-pwm modes , the action can be forced to have immediate effect by using the foc1x strobe bits. 12.8 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of waveform generation mode bits (pwm1a, pwm1b, and wgm1[1:0]) and compare output mode bits (com1x[1:0]). the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com1x[1:0] bits control whether the pwm output generated should be inverted, non-inverted or complementary. for non-pwm modes the com1x[1:0] bits control whether the output should be set, cleared, or toggled at a compare match. 12.8.1 normal mode the simplest mode of operation is normal mode (pwm1a/pwm1b = 0), where the counter counts from bottom to top (defined as ocr1c) then restarts from bottom. the ocr1c defines the top value for the counter, hence also its resolution, and allows control of the com- pare match output frequency. in toggle compare output mode the waveform output (ocw1x) is toggled at compare match between tcnt1 and ocr1x. in non-inverting compare output mode the waveform output is cleared on the compare match. in inverting compare output mode the waveform output is set on compare match. the timing diagram for normal mode is shown in figure 12-11 . figure 12-11. normal mode, timing diagram tcntn ocwnx (comnx=1) ocnx interrupt flag set 1 4 period 2 3 tovn interrupt flag set 99 8197c?avr?05/11 attiny261a/461a/861a the counter value (tcnt1) that is shown as a histogram in figure 12-11 is incremented until the counter value matches the top va lue. the counter is then clea red at the following clock cycle the diagram includes the waveform output (ocw1x) in toggle compare mode. the small hori- zontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the timer/counter overflow flag (tov1) is se t in the same clock cycle as the tcnt1 becomes zero. the tov1 flag in this case behaves like a 11t h bit, except that it is only set, not cleared. however, combined with the timer overflow inte rrupt, that automatically clears the tov1 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. for generating a waveform, the ocw1x output can be set to toggle its logical level on each compare match by setting the compare output mode bits to tog- gle mode (com1x[1:0] = 1). the oc1x value will not be visible on the port pin unless the data direction for the pin is set to output. the wa veform generated will have a maximum frequency of f oc1x = f clkt1 /4 when ocr1c is set to zero. the waveform frequency is defined by the following equation: resolution, r pwm , shows how many bit is required to express the value in the ocr1c register and it can be calculated using the following equation: the output compare pin configurations in normal mode are described in table 12-2 . 12.8.2 fast pwm mode the fast pulse width modulation or fast pwm mode (pwm1a/pwm1b = 1 and wgm1[1:0] = 00) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top (defined as ocr1c) then restarts from bottom. in non-inverting compare output mode the waveform output (ocw1x) is cleared on the compare match between tcnt1 and ocr1x and set at bottom. in inverting compare output mode, the waveform output is set on compare match and cleared at bottom. in complementary compare output mode the waveform output is cleared on the compare match and set at bottom. due to the single-slope operation, the operatin g frequency of the fast pwm mode can be twice as high as the phase and frequency correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and table 12-2. output compare pin configurations in normal mode com1x1 com1x0 oc1x pin oc1x pin 0 0 disconnected disconnected 0 1 disconnected oc1x 1 0 disconnected oc1x 1 1 disconnected oc1x f oc1x f clkt1 21ocr1c + () ? ------------------------------------------ - = r pwm log 2 ocr1c 1 + () = 100 8197c?avr?05/11 attiny261a/461a/861a dac applications. high frequency allows physicall y small sized external components (coils, capacitors), and therefore reduces total system cost. the timing diagram for the fast pwm mode is shown in figure 12-12 . the counter is incre- mented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes the waveform output in non- inverted and inverted compare output modes. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. figure 12-12. fast pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc1x pins. setting the com1x[1:0] bits to two will produce a non-inverted pwm and setting the com1x[1:0] to three will produce an inverted pwm output. setting the com1 x[1:0] bits to one will enable complementary compare output mode and produce both the non-inverted (oc1x) and inverted output (oc1x ). the actual value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by setting (or clearing) the waveforn output (ocw1x) at the compare match between ocr1x and tcnt1, and clearing (or setting) the waveform output at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the number of steps in single-slope operation. the value of n equals either to the top value. the extreme values for the ocr1c register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1c is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr1c equal to max will result tcntn ocrnx up dat e and tovn i n t er r u p t fl ag set 1 pe r i o d 2 3 ocwnx ocwnx (comnx[1:0] = 2) (comnx[1:0] = 3) ocrnx int errup t fl ag set 4 5 6 7 f ocnxpwm f clkt1 n ------------ - = 101 8197c?avr?05/11 attiny261a/461a/861a in a constantly high or low output (depending on the polarity of the output set by the com1x[1:0] bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting the waveform output (ocw1x) to toggle its logical level on each compare match (com1x[1:0] = 1). the waveform generated will have a maximum frequency of f oc1 = f clkt1 /4 when ocr1c is set to three. the general i/o port function is overridden by the output compare value (oc1x / oc1x ) from the dead time generator, if either of the com1x[1:0] bits are set and the data direction regis- ter bits for the oc1x and oc1x pins are set as an output. if the com1x[1:0] bits are cleared, the actual value from the port regist er will be visible on the port pin. the output compare pin config- urations are described in table 12-3 . 12.8.3 phase and frequency correct pwm mode the phase and frequency correct pwm mode (pwm1a/pwm1b = 1 and wgm1[1:0] = 01) pro- vides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is bas ed on a dual-slope operation. the counter counts repeatedly from bottom to top (defined as ocr1c) and then from top to bottom. in non-inverting compare output mode the wave form output (ocw1x) is cleared on the com- pare match between tcnt1 and ocr1x while upcounting, and set on the compare match while down-counting. in inverting output compare mode, the operation is inverted. in complementary compare output mode, the waveform ouput is cleared on the compare match and set at bot- tom. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feat ure of the dual-slope pwm modes, these modes are preferred for motor control applications. the timing diagram for the phase and frequency correct pwm mode is shown on figure 12-13 in which the tcnt1 value is shown as a histogra m for illustrating the dua l-slope operation. the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt1 value w ill be equal to top for one timer clock cycle. the diagram includes the waveform output (ocw1x) in non-inverted and inverted compare output mode. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. table 12-3. output compare pin configurations in fast pwm mode com1x1 com1x0 oc1x pin oc1x pin 0 0 disconnected disconnected 0 1 oc1x oc1x 1 0 disconnected oc1x 1 1 disconnected oc1x 102 8197c?avr?05/11 attiny261a/461a/861a figure 12-13. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in the phase and frequency correct pwm mode, the compare unit allows generation of pwm waveforms on the oc1x pins. setting the com1x[ 1:0] bits to two will produce a non-inverted pwm and setting the com1x[1:0] to three will produce an inverted pwm output. setting the com1a[1:0] bits to one will enab le complementary comp are output mode a nd produce both the non-inverted (oc1x) and inverted output (oc1x ). the actual values will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the waveform output (ocw1x) at the compare match between ocr1x and tcnt1 when the counter increments, and setting (or clearing) the waveform output at compare match when the counter decrements. the pwm fr equency for the output when using the phase and frequency correct pwm can be calculated by the following equation: the n variable represents the number of steps in dual-slope operation. the value of n equals to the top value. the extreme values for the ocr1c register represent special cases when generating a pwm waveform output in the phase and frequency correct pwm mode. if the ocr1c is set equal to bottom, the output will be continu ously low and if set equal to max the output will be continu- ously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. the general i/o port function is overridden by the output compare value (oc1x / oc1x ) from the dead time generator, if either of the com1x[1:0] bits are set and the data direction regis- ter bits for the oc1x and oc1x pins are set as an output. if the com1x[1:0] bits are cleared, the tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocwnx ocwnx (comnx = 2) (comnx = 3) ocrnx update f ocnxpcpwm f clkt1 n ------------ - = 103 8197c?avr?05/11 attiny261a/461a/861a actual value from the port register will be visible on the port pin. the conf igurations of the output compare pins are described in table 12-4 . 12.8.4 pwm6 mode the pwm6 mode (pwm1a = 1, wgm1[1:0] = 1x) provide pwm waveform generation option e.g. for controlling brushless dc (bldc) motors . in the pwm6 mode the ocr1a register con- trols all six output compare waveforms as the same waveform output (ocw1a) from the waform generator is used for generating all waveforms. the pwm6 mode also provides an out- put compare override enable register (oc1oe) t hat can be used with an instant response for disabling or enabling the output compare pins. if the output compare override enable bit is cleared, the actual value from the port register will be visible on the port pin. the pwm6 mode provides two counter operation modes, a single-slope operation and a dual- slope operation. if the single-slope operation is selected (the wgm10 bit is set to 0), the counter counts from bottom to top (defined as ocr1c) then restart from bottom like in fast pwm mode. the pwm waveform is generated by setting (or clearing) the waveforn output (ocw1a) at the compare match between ocr1a and tcnt1, and clearing (or setting) the waveform output at the timer clock cycle the counter is cleared (changes from top to bottom). the timer/counter overflow flag (tov1) is set each time the counter reaches the top and, if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. whereas, if the dual-slope operation is selected (the wgm10 bit is set to 1), the counter counts repeatedly from bottom to top (defined as ocr1c) and then from top to bottom like in phase and frequency correct pwm mode. the pwm waveform is generated by setting (or clearing) the waveforn output (ocw1a) at the compare match between ocr1a and tcnt1 when the counter increments, and clearing (or setting) the waveform output at the he compare match between ocr1a and tcnt1 when the coun ter decrements. the timer/counter overflow flag (tov1) is set each time the counter reaches the bottom and, if the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. the timing diagram for the pwm6 mode in single-slope operation when the com1a[1:0] bits are set to ?10? is shown in figure 12-14 . the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the tcnt1 value is in the timing diagram shown as a histogram for illustrating th e single-slope ope ration. the tim- ing diagram includes output compare pins oc1a and oc1a, and the corresponding output compare override enable bits (oc1oe1:oc1oe0). table 12-4. output compare pin configurations in phase and frequency correct pwm mode com1x1 com1x0 oc1x pin oc1x pin 0 0 disconnected disconnected 0 1 oc1x oc1x 1 0 disconnected oc1x 1 1 disconnected oc1x 104 8197c?avr?05/11 attiny261a/461a/861a figure 12-14. pwm6 mode, single-slope operation, timing diagram the general i/o port function is overridden by the output compare value (oc1x / oc1x ) from the dead time generator if either of the com1x[1:0] bits are set. the output compare pins can also be overriden by the output compare override enable bits oc1oe5:oc1oe0. if an over- ride enable bit is cleared, the actual value from the port register will be visible on the port pin and, if the override enable bit is set, the output compare pin is allowed to be connected on the port pin. the output compare pin configurations are described in table 12-5 , table 12-6 and table 12-7 . table 12-5. configuration of output compare pins oc1a and oc1a in pwm6 mode com1a1 com1a0 oc1a pin (pb0) oc1a pin (pb1) 0 0 disconnected disconnected 01oc1a ? oc1oe0 oc1a ? oc1oe1 10oc1a ? oc1oe0 oc1a ? oc1oe1 11oc1a ? oc1oe0 oc1a ? oc1oe1 table 12-6. configuration of output compare pins oc1b and oc1b in pwm6 mode com1b1 com1b0 oc1b pin (pb2) oc1b pin (pb3) 0 0 disconnected disconnected 01oc1a ? oc1oe2 oc1a ? oc1oe3 10oc1a ? oc1oe2 oc1a ? oc1oe3 11oc1a ? oc1oe2 oc1a ? oc1oe3 tcnt1 oc1a pin oc1a pin oc1b pin oc1b pin oc1d pin oc1d pin oc1oe0 oc1oe1 oc1oe2 oc1oe3 oc1oe4 oc1oe5 ocw1a 105 8197c?avr?05/11 attiny261a/461a/861a 12.9 timer/counter timing diagrams the timer/counter is a synchron ous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 12-15 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase and frequency correct pwm mode. figure 12-15. timer/counter timing diagram, no prescaling figure 12-16 shows the same timing data, but with the prescaler enabled, in all modes other than phase and frequency correct pwm mode. figure 12-16. timer/counter timing dia gram, with prescaler (f clkt1 /8) figure 12-17 shows the setting of ocf1a, ocf1b and ocf1d in all modes. table 12-7. configuration of output compare pins oc1d and oc1d in pwm6 mode com1d1 com1d0 oc1d pin (pb4) oc1d pin (pb5) 0 0 disconnected disconnected 01oc1a ? oc1oe4 oc1a ? oc1oe5 10oc1a ? oc1oe4 oc1a ? oc1oe5 11oc1a ? oc1oe4 oc1a ? oc1oe5 clk tn (clk pck /1) tovn clk pck tcntn top - 1 top bottom bottom + 1 tovn tcntn top - 1 top bottom bottom + 1 clk pck clk tn (clk pck /8) 106 8197c?avr?05/11 attiny261a/461a/861a figure 12-17. timer/counter timing diagram, setting of ocf1x, with prescaler (f clkt1 /8) figure 12-18 shows the setting of tov1 in phase and frequency correct pwm mode. figure 12-18. timer/counter timing dia gram, with prescaler (f clkt1 /8) 12.10 fault protection unit the timer/counter1 incorporates a fault protection unit, which can be set to disable the pwm output pins when an external event is triggered. the external signal indicating an event can be applied via the external interrupt int0 pin or, alternatively, via the analog-comparator unit. the fault protection uni t is illustrated in figure 12-19 . the elements of the block diagram that are not directly a part of the fault protection unit are gray shaded. figure 12-19. fault protection unit block diagram fault protection mode is enabled by setting the fault protection enable (fpen1) bit and trig- gered by a change in logic level at external inte rrupt pin (int0). alternatively, fault protection mode can be triggered by the analog comparator output (aco). when fault protection is triggered, the com1x bits are cleared, output comparators are discon- nected from the pwm output pins and portb r egister bits are connected to the pwm output ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk pck clk tn (clk pck /8) tovn tcntn bottom + 1 bottom + 1 bottom bottom + 1 clk pck clk tn (clk pck /8) analog comparator noise canceler int0 edge detector fpac1 fpnc1 fpes1 aco* fpen1 timer/counter1 fault_protection (int. req.) 107 8197c?avr?05/11 attiny261a/461a/861a pins. the fault protection enable (fpen1) is automatically cleared at the same system clock as the com1nx bits are cleared. if the fault protection interrupt enable bit (fpie1) is set, a fault protection interrupt is generated and the fpen1 bit is cleared. alternatively the fpen1 bit can be polled by software to figure out when the timer/counter has entered to fault protection mode. 12.10.1 fault protection trigger source the main trigger source for the fault protection unit is the external interrupt pin (int0). alterna- tively the analog comparator output can be used as trigger source for the fault protection unit. the analog comparator is selected as trigger source by setting the fault protection analog comparator (fpac1) bit in the timer/counter1 control register (tccr1d). be aware that changing trigger source can trigger a fault protection mode. therefore it is recommended to clear the fpf1 flag after changing trigger sour ce, setting edge detector or enabling the fault protection. both the external interrupt pin (int0) and the analog comparator output (aco) inputs are sam- pled using the same technique as with the t0 pin (see figure 11-3 on page 73 ). the edge detectors are also identical but when the noise ca nceler is enabled additional logic is activated before the edge detector, increasing the propagation delay with four system clock cycles. an input capture can also be tr iggered by software by controlling the port of the int0 pin. 12.10.2 noise canceler the noise canceler uses a simple digital filter ing technique to improve noise immunity. consecu- tive samples are monitored in a pipeline four units deep. the signal going to the edge detecter is allowed to change only when all four samples are equal. the noise canceler is enabled by setting the f ault protection noise canceler (fpnc1) bit in timer/counter1 control register d (tccr1d). when enabled, the noise canceler introduces an additional delay of four system clock cycles to a change applied to the input. the noise canceler uses the system clock directly and is therefore not affected by the prescaler. 12.11 accessing 10-bit registers if 10-bit values are written to the tcnt1 and ocr1a/b/c/d registers, the 10-bit registers can be byte accessed by the avr cpu via the 8-bit da ta bus using two read or write operations. the 10-bit registers have a common 2-bit timer/counter1 high byte register (tc1h) that is used for temporary storing of the two msbs of the 10-bi t access. the same tc1h register is shared between all 10-bit registers. accessing the low byte triggers the 10-bit read or write operation. when the low byte of a 10-bit register is written by the cpu, the high byte stored in the tc1h register, and the low byte written are both copied into the 10-bit register in the same clock cycle. when the low byte of a 10-bit register is read by the cpu, the high byte of the 10-bit register is copied into the tc1h register in the same clock cycle as the low byte is read. to do a 10-bit write, the high byte must be written to the tc1h register before the low byte is written. for a 10-bit read, the low byte must be read before the high byte. 12.11.1 reusing the temporary high byte register if writing to more than one 10-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. 108 8197c?avr?05/11 attiny261a/461a/861a 12.11.2 code examples the following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the tc1h register. the same pr inciple can be used directly for accessing the ocr1a/b/c/d registers. note: see ?code examples? on page 6 . the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 10-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 10-bit register, and the interrupt code updates the tc1h register by accessing the same or any other of the 10-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the tc1h regi ster, the main code must disable the interrupts during the 16-bit access. assembly code example ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tc 1 h,r17 out tcnt 1 ,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 in r17,tc 1 h ... c code example unsigned int i; ... /* set tcnt1 to 0x01ff */ tc1h = 0x01; tcnt1 = 0xff; /* read tcnt1 into i */ i = tcnt1; i |= (( unsigned int )tc1h << 8); ... 109 8197c?avr?05/11 attiny261a/461a/861a the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b/c/d registers can be done by using the same principle. note: see ?code examples? on page 6 . the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example tim1_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 in r17,tc 1 h ; restore global interrupt flag out sreg,r18 ret c code example unsigned int tim1_readtcnt1( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt1 into i */ i = tcnt1; i |= ((unsigned int)tc1h << 8); /* restore global interrupt flag sreg = sreg; return i; } 110 8197c?avr?05/11 attiny261a/461a/861a the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b/c/d registers can be done by using the same principle. note: see ?code examples? on page 6 . the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt1. assembly code example tim1_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tc 1 h,r17 out tcnt 1 ,r16 ; restore global interrupt flag out sreg,r18 ret c code example void tim1_writetcnt1( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt1 to i */ tc1h = (i >> 8); tcnt1 = (unsigned char)i; /* restore global interrupt flag */ sreg = sreg; } 111 8197c?avr?05/11 attiny261a/461a/861a 12.12 register description 12.12.1 tccr1a ? timer/counter1 control register a ? bits 7:6 ? com1a[1:0]: comparator a output mode, bits 1 and 0 these bits control the behaviour of the wave form output (ocw1a) and the connection of the output compare pin (oc1a). if one or both of the com1a[1:0] bits are set, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. the complementary oc1b output is connected only in pwm modes when the com1a[1:0] bits are set to ?01?. note that the data direction register (d dr) bit corresponding to the oc1a and oc1a pins must be set in order to enable the output driver. the function of the com1a[1:0] bits depends on the pwm1a, wgm10 and wgm11 bit settings. table 12-8 shows the com1a[1:0] bit functionality when the pwm1a bit is set to normal mode (non-pwm). table 12-9 shows the com1a[1:0] bit functionality when the pwm1a, wgm10 and wgm11 bits are set to fast pwm mode. bit 76543210 0x30 (0x50) com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b tccr1a read/write r/w r/w r/w r/w w w r/w r/w initial value00000000 table 12-8. compare output mode, normal mode (non-pwm) com1a[1:0] ocw1a behaviour oc1a pin oc1a pin 00 normal port operation. disconnected disconnected 01 toggle on compare match. connected disconnected 10 clear on compare match. connected disconnected 11 set on compare match. connected disconnected table 12-9. compare output mode, fast pwm mode com1a[1:0] ocw1a behaviour oc1a oc1a 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. connected connected 10 cleared on compare match. set when tcnt1 = 0x000. connected disconnected 11 set on compare match cleared when tcnt1 = 0x000. connected disconnected 112 8197c?avr?05/11 attiny261a/461a/861a table 12-10 shows the com1a[1:0] bit functionality when the pwm1a, wgm10 and wgm11 bits are set to phase and frequency correct pwm mode. table 12-11 shows the com1a[1:0] bit functionality when the pwm1a, wgm10 and wgm11 bits are set to single-slope pwm6 mode. in the pwm6 mode the same waveform output (ocw1a) is used for generating all waveforms and the output compare values oc1a and oc1a are connected on thw all oc1x and oc1x pins as described below. table 12-12 shows the com1a[1:0] bit functionality when the pwm1a, wgm10 and wgm11 bits are set to dual-slope pwm6 mode.i bits com1a1 and com1a0 are shadowed in tccr1c. writing to bits com1a1 and com1a0 will also change bits com1a1s and com1a0s in tccr1c. similary, ch anges written to bits com1a1s and com1a0s in tccr1c will show here. see ?tccr1c ? timer/counter1 control register c? on page 116 . table 12-10. compare output mode, phase and frequency correct pwm mode com1a[1:0] ocw1a behaviour oc1a pin oc1a pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. connected connected 10 cleared on compare match when up-counting. set on compare match when down-counting. connected disconnected 11 set on compare match when up-counting. cleared on compare match when down-counting. connected disconnected table 12-11. compare output mode, single-slope pwm6 mode com1a[1:0] ocw1a behaviour oc1x pin oc1x pin 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. oc1a oc1a 10 cleared on compare match. set when tcnt1 = 0x000. oc1a oc1a 11 set on compare match. cleared when tcnt1 = 0x000. oc1a oc1a table 12-12. compare output mode, dual-slope pwm6 mode com1a[1:0] ocw1a behaviour oc1x pin oc1x pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. oc1a oc1a 10 cleared on compare match when up-counting. set on compare match when down-counting. oc1a oc1a 11 set on compare match when up-counting. cleared on compare match when down-counting. oc1a oc1a 113 8197c?avr?05/11 attiny261a/461a/861a ? bits 5:4 ? com1b[1:0]: comparator b output mode, bits 1 and 0 these bits control the behaviour of the wave form output (ocw1b) and the connection of the output compare pin (oc1b). if one or both of the com1b[1:0] bits are set, the oc1b output overrides the normal port functionality of the i/o pin it is connected to. the complementary oc1b output is connected only in pwm modes when the com1b[1:0] bits are set to ?01?. note that the data direction register (ddr) bit corresponding to the oc 1b pin must be set in order to enable the output driver. the function of the com1b[1:0] bits depends on the pwm1b and wgm1[1:0] bit settings. table 12-13 shows the com1b[1:0] bit functionality when the pwm1b bit is set to normal mode (non- pwm). table 12-14 shows the com1b[1:0] bit functionalit y when the pwm1b and wgm1[1:0] bits are set to fast pwm mode. table 12-15 shows the com1b[1:0] bit functionalit y when the pwm1b and wgm1[1:0] bits are set to phase and frequency correct pwm mode. bits com1b1 and com1b0 are shadowed in tccr1c. writing to bits com1b1 and com1b0 will also change bits com1b1s and com1b0s in tccr1c. similary, ch anges written to bits table 12-13. compare output mode, normal mode (non-pwm) com1b[1:0] ocw1b behaviour oc1b pin oc1b pin 00 normal port operation. disconnected disconnected 01 toggle on compare match. connected disconnected 10 clear on compare match. connected disconnected 11 set on compare match. connected disconnected table 12-14. compare output mode, fast pwm mode com1b[1:0] ocw1b behaviour oc1b pin oc1b pin 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1 = 0x000. connected connected 10 cleared on compare match. set when tcnt1 = 0x000. connected disconnected 11 set on compare match. cleared when tcnt1 = 0x000. connected disconnected table 12-15. compare output mode, phase and frequency correct pwm mode com1b[1:0] ocw1b behaviour oc1b pin oc1b pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. connected connected 10 cleared on compare match when up-counting. set on compare match when down-counting. connected disconnected 11 set on compare match when up-counting. cleared on compare match when down-counting. connected disconnected 114 8197c?avr?05/11 attiny261a/461a/861a com1b1s and com1b0s in tccr1c will show here. see ?tccr1c ? timer/counter1 control register c? on page 116 . ? bit 3 ? foc1a: force output compare match 1a the foc1a bit is only active when the pwm1a bit specify a non-pwm mode. writing a logical one to this bit forces a change in the waveform output (ocw1a) and the out- put compare pin (oc1a) according to the values already set in com1a1 and com1a0. if com1a1 and com1a0 written in the same cycle as foc1a, the new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1a1 and com1a0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1a bit always reads zero. ? bit 2 ? foc1b: force output compare match 1b the foc1b bit is only active when the pwm1b bit specify a non-pwm mode. writing a logical one to this bit forces a change in the waveform output (ocw1b) and the out- put compare pin (oc1b) according to the values already set in com1b1 and com1b0. if com1b1 and com1b0 written in the same cycle as foc1b, the new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1b1 and com1b0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1b bit always reads zero. ? bit 1 ? pwm1a: pulse width modulator a enable when set (one) this bit enables pwm mode based on comparator ocr1a ? bit 0 ? pwm1b: pulse width modulator b enable when set (one) this bit enables pwm mode based on comparator ocr1b. 12.12.2 tccr1b ? timer/counter1 control register b ? bit 7 ? pwm1x: pwm inversion mode when this bit is set (one), the pwm inversion mode is selected and the dead time generator outputs, oc1x and oc1x are inverted. ? bit 6 ? psr1: prescaler reset timer/counter1 when this bit is set (one), the timer/counter1 pr escaler (tcnt1 is unaffe cted) will be reset. the bit will be cleared by hard ware after the operation is performed. writing a zero to this bit will have no effect. this bit will always read as zero. ? bits 5:4 ? dtps1[1:0]: dead time prescaler bits the timer/counter1 control register b is a 8-bit read/write register. bit 76543210 0x2f (0x4f) pwm1x psr1 dtps11 dtps10 cs13 cs12 cs11 cs10 tccr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 115 8197c?avr?05/11 attiny261a/461a/861a the dedicated dead time prescaler in front of the dead time generator can divide the timer/counter1 clock (pck or ck) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. the dead time prescaler is controlled by two bits dtps11 and dtps10 from the dead time prescaler register. these bits define the division factor of the dead time prescaler. the division factors are given in table 12-16 . ? bits 3:0 ? cs1[3:0]: clock select bits 3 - 0 the clock select bits 3, 2, 1, and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable function. table 12-16. division factors of the dead time prescaler dtps11 dtps10 prescaler divi des the t/c1 clock by 0 0 1x (no division) 012x 104x 118x table 12-17. timer/counter1 prescaler select cs13 cs12 cs11 cs10 asynchronous clocki ng mode synchronous clocking mode 0000t/c1 stopped t/c1 stopped 0001pck ck 0010pck/2 ck/2 0011pck/4 ck/4 0100pck/8 ck/8 0101pck/16 ck/16 0110pck/32 ck/32 0111pck/64 ck/64 1000pck/128 ck/128 1001pck/256 ck/256 1010pck/512 ck/512 1011pck/1024 ck/1024 1100pck/2048 ck/2048 1101pck/4096 ck/4096 1110pck/8192 ck/8192 1111pck/16384 ck/16384 116 8197c?avr?05/11 attiny261a/461a/861a 12.12.3 tccr1c ? timer/counter1 control register c ? bits 7:6 ? com1a1s, com1a0s: comparator a output mode, shadow bits 1 and 0 these are shadow bits of com1a1 and com1a0 in tccr1a. writing to bits com1a1s and com1a0s will also change bits com1a1 and com1a0 in tccr1a. similary, changes written to bits com1a1 and com1a0 in tccr1a will show here. see ?tccr1a ? timer/counter1 control register a? on page 111 for information on bit usage. ? bits 5:4 ? com1b1s, com1b0s: comparator b output mode, shadow bits 1 and 0 these are shadow bits of com1b1 and com1b0 in tccr1a. writing to bits com1b1s and com1b0s will also change bits com1b1 and com1b0 in tccr1a. similary, changes written to bits com1b1 and com1b0 in tccr1a will show here. see ?tccr1a ? timer/counter1 control register a? on page 111 for information on bit usage. ? bits 3:2 ? com1d[1:0]: comparator d output mode, bits 1 and 0 these bits control the behaviour of the wave form output (ocw1d) and the connection of the output compare pin (oc1d). if one or both of the com1d[1:0] bits are set, the oc1d output overrides the normal port functionality of the i/o pin it is connected to. the complementary oc1d output is connected only in pwm modes when the com1d[1:0] bits are set to ?01?. note that the data direction register (ddr) bit corres ponding to the oc1d pin must be set in order to enable the output driver. the function of the com1d[1:0] bits depends on the pwm1d and wgm1[1:0] bit settings. table 12-18 shows the com1d[1:0] bit functionality when the pwm1d bit is set to a normal mode (non-pwm). table 12-19 shows the com1d[1:0] bit functionality when the pwm1d and wgm1[1:0] bits are set to fast pwm mode. bit 76543210 0x27 (0x47) com1a1s com1a0s com1b1s com1b0s com1d1 com1d0 foc1d pwm1d tccr1c read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 12-18. compare output mode, normal mode (non-pwm) com1d[1:0] ocw1d behaviour oc1d pin oc1d pin 00 normal port operation. disconnected disconnected 01 toggle on compare match. connected disconnected 10 clear on compare match. connected disconnected 11 set on compare match. connected disconnected table 12-19. compare output mode, fast pwm mode com1d[1:0] ocw1d behaviour oc1d pin oc1d pin 00 normal port operation. disconnected disconnected 01 cleared on compare match. set when tcnt1=0x000. connected connected 10 cleared on compare match. set w hen tcnt1=0x000. connected disconnected 11 set on compare match. cleared when tcnt1=0x000. connected disconnected 117 8197c?avr?05/11 attiny261a/461a/861a table 12-20 shows the com1d[1:0] bit functionality when the pwm1d and wgm1[1:0] bits are set to phase and frequency correct pwm mode. ? bit 1 ? foc1d: force output compare match 1d the foc1d bit is only active when the pwm1d bit specify a non-pwm mode. writing a logical one to this bit forces a change in the waveform output (ocw1d) and the out- put compare pin (oc1d) according to the values already set in com1d1 and com1d0. if com1d1 and com1d0 written in the same cycle as foc1d, th e new settings will be used. the force output compare bit can be used to change the output pin value regardless of the timer value. the automatic action programmed in com1d1 and com1d0 takes place as if a compare match had occurred, but no interrupt is generated. the foc1d bit is always read as zero. ? bit 0 ? pwm1d: pulse width modulator d enable when set (one) this bit enables pwm mode based on comparator ocr1d. 12.12.4 tccr1d ? timer/counter1 control register d ? bit 7 ? fpie1: fault protection interrupt enable setting this bit (to one) enables the fault protection interrupt. ? bit 6 ? fpen1: fault protection mode enable setting this bit (to one) activates the fault protection mode. ? bit 5 ? fpnc1: fault protection noise canceler setting this bit activates the fault protection no ise canceler. when the noi se canceler is acti- vated, the input from the fault protection pin (int0) is filtered. the filter function requires four successive equal valued samples of the int0 pin for changing its output. the fault protection is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 4 ? fpes1: fault protection edge select this bit selects which edge on the fault protecti on pin (int0) is used to trigger a fault event. when the fpes1 bit is written to zero, a falling (negative) edge is used as trigger, and when the fpes1 bit is written to one, a rising (positive) edge will trigger the fault. table 12-20. compare output mode, phase and frequency correct pwm mode com1d[1:0] ocw1d behaviour oc1d pin oc1d pin 00 normal port operation. disconnected disconnected 01 cleared on compare match when up-counting. set on compare match when down-counting. connected connected 10 cleared on compare match when up-counting. set on compare match when down-counting. connected disconnected 11 set on compare match when up-counting. cleared on compare match when down-counting. connected disconnected bit 76543210 0x26 (0x46) fpie1 fpen1 fpnc1 fpes1 fpac1 fpf1 wgm11 wgm10 tccr1d read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 118 8197c?avr?05/11 attiny261a/461a/861a ? bit 3 ? fpac1: fault protection analog comparator enable when written logic one, this bit enables the fault protection function in timer/counter1 to be triggered by the analog comparator. the comparator output is in this case directly connected to the fault protection front-end logic, making the comparator utilize the noise canceler and edge select features of the timer/counter1 fault protection interrupt. when written logic zero, no con- nection between the analog comparator and the fault protection function exists. to make the comparator trigger the timer/counter1 fault protection interrupt, the fpie1 bit in the timer/counter1 control regist er d (tccr1d) must be set. ? bit 2 ? fpf1: fault protection interrupt flag when the fpie1 bit is set (one), the fault protec tion interrupt is enabled. activity on the pin will cause an interrupt request even, if the fault protec tion pin is configured as an output. the corre- sponding interrupt of fault protection interrupt request is executed from the fault protection interrupt vector. the bit fpf1 is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, fpf1 is clea red after a synchronization clock cycle by writing a logical one to the flag. when the sreg i-bit, fpie1 and fpf1 are set, the fault interrupt is executed. ? bits 1:0 ? wgm1[1:0]: waveform generation mode bits these bits together with the pwm1a/pwm1b bits control the counting sequence of the counter and the type of waveform generation to be used, as shown in table 12-21 . modes of operation supported by the timer/counter1 are: normal mode (counter), fast pwm mode, phase and fre- quency correct pwm and pwm6 modes. 12.12.5 tccr1e ? timer/counter1 control register e ? bits 7:6 ? res: reserved bits these bits are reserved and always read zero. ? bits 5:0 ? oc1oe[5:0]: output compare override enable bits these bits are the ouput compare override enable bits that are used to connect or disconnect the output compare pins in pwm6 modes with an instant response on the corresponding out- put compare pins. the actual value from the port register will be visi ble on the port pin, when table 12-21. waveform generation mode bit description pwm1a/ pwm1b wgm1[1:0] timer/counter mode of operation top update ocr1x at set tov1 flag at 0 xx normal ocr1c immediate top 1 00 fast pwm ocr1c top top 1 01 phase & frequency correct pwm ocr1c bottom bottom 1 10 pwm6 / single-slope ocr1c top top 1 11 pwm6 / dual-slope ocr1c bottom bottom bit 76543210 0x00 (0x20) - - oc1oe5 oc1oe4 oc1oe3 oc1oe2 oc1oe1 oc1oe0 tccr1e read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 119 8197c?avr?05/11 attiny261a/461a/861a the output compare override enable bit is cleared. table 12-22 shows the output compare override enable bits and their co rresponding output compare pins. 12.12.6 pllcsr ? pll control and status register ? bit 7 ? lsm: low speed mode the low speed mode is set, if the lsm bit is written to one. then the fast peripheral clock is scaled down to 32 mhz. the low speed mode must be set, if the supply voltage is below 2.7 volts, because the timer/counter1 is not running fast enough on low voltage levels. it is recom- mended that the timer/counter1 is sto pped whenever the lsm bit is changed. note, that lsm can not be set if pll clk is used as a system clock. ? bit 6:3 ? res : reserved bits these bits are reserved and always read zero. ? bit 2 ? pcke: pck enable the pcke bit change the timer/counter1 clock source. when it is set, the asynchronous clock mode is enabled and fast 64 mhz (or 32 mhz in low speed mode) pck clock is used as a timer/counter1 clock source. if this bit is cl eared, the synchronous clock mode is enabled, and system clock ck is used as timer/counter1 clock source. it is safe to set this bit only when the pll is locked i.e the plock bit is 1. note that the pcke bit can be set only, if the pll has been enabled earlier. the pll is enabled when t he cksel fuse has been programmed to 0x0001 (the pll clock mode is selected) or the plle bit has been set to one. ? bit 1 ? plle: pll enable when the plle is set, the pll is started and if needed internal oscillator is started as a pll ref- erence clock. if pll is selected as a system clock source the value for this bit is always 1. ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock. the plock bit should be ignored during initial pll lock-in sequence when pll frequency overshoots and undershoots, before reaching steady state. the steady state is obtained within 100 s. after pll lock-in it is recommended to check the plock bit before enabling pck for timer/counter1. table 12-22. output compare override enable bits vs. output compare pins output compareoverride enable bit output compare output output compare pin oc1oe0 oc1a pb0 oc1oe1 oc1a pb1 oc1oe2 oc1b pb2 oc1oe3 oc1b pb3 oc1oe4 oc1d pb4 oc1oe5 oc1d pb5 bit 76543210 0x29 (0x49) lsm????pckeplleplockpllcsr read/writer/wrrrrr/wr/wr initial value0000000/10 120 8197c?avr?05/11 attiny261a/461a/861a 12.12.7 tcnt1 ? timer/counter1 this 8-bit register contains the value of timer/counter1. the timer/counter1 is realized as a 10-bit up/ down counter with read and write access. due to synchronization of the cpu, timer/counter1 data written into timer/counter1 is delayed by one and half cpu clock cycles in syn chronous mode and at most o ne cpu clock cycles for asyn- chronous mode. when a 10-bit accuracy is preferred, special procedures must be followed for accessing the 10-bit tcnt1 register via t he 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 107 . alternatively the timer/counter1 can be used as an 8-bit timer/counter. note that the timer/counter1 always starts counting up after writing the tcnt1 register. 12.12.8 tc1h ? timer/counter1 high byte the temporary timer/counter1 register is an 2-bit read/write register. ? bits 7:2 ? res: reserved bits these bits are reserved and always reads zero. ? bits 1:0 ? tc19, tc18: two msb bits of the 10-bit accesses if 10-bit accuracy is used, the timer/counter1 high byte register (tc1h) is used for temporary storing the msb bits (tc19, tc18) of the 10-bit acceses. the same tc1h register is shared between all 10-bit registers within the timer/counter1. note that special procedures must be fol- lowed when accessing the 10-bit tcnt1 register via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 107 . 12.12.9 ocr1a ? timer/counter1 output compare register a the output compare register a is an 8-bit read/write register. the timer/counter output compare register a contains data to be continuously compared with timer/counter1. actions on compare matches are specified in tccr1a. a compare match does only occur if timer/counter1 counts to the ocr1a value. a software write that sets tcnt1 and ocr1a to the same value does not generate a compare match. a compare match will set the compar e interrupt flag ocf1a after a synchronization delay follow- ing the compare event. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit ouput compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 107 . bit 76543210 0x2e (0x4e) msb lsb tcnt1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x25 (0x45) ?????? tc19 tc18 tc1h read/writerrrrrrr/wr/w initial value00000000 bit 76543210 0x2d (0x4d) msb lsb ocr1a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 121 8197c?avr?05/11 attiny261a/461a/861a 12.12.10 ocr1b ? timer/counter1 output compare register b the output compare register b is an 8-bit read/write register. the timer/counter output compare register b contains data to be continuously compared with timer/counter1. actions on compare matches are specified in tccr1. a compare match does only occur if timer/counter1 counts to the ocr1b value. a software write that sets tcnt1 and ocr1b to the same value does not generate a compare match. a compare match will set the compar e interrupt flag ocf1b after a synchronization delay follow- ing the compare event. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 107 . 12.12.11 ocr1c ? timer/counter1 output compare register c the output compare register c is an 8-bit read/write register. the timer/counter output compare register c co ntains data to be continuously compared with timer/counter1, and a compare ma tch will clear tcnt1. this regist er has the same function in normal mode and pwm modes. note that, if a smaller value than three is written to the output compare register c, the value is automatically replaced by three as it is a minumu m value allowed to be written to this register. note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 107 . 12.12.12 ocr1d ? timer/counter1 output compare register d the output compare register d is an 8-bit read/write register. the timer/counter output compare register d co ntains data to be continuously compared with timer/counter1. actions on compare matches are specified in tccr1a. a compare match does only occur if timer/counter1 counts to the ocr1d value. a software write that sets tcnt1 and ocr1d to the same value does not generate a compare match. a compare match will set the compar e interrupt flag ocf1d after a synchronization delay follow- ing the compare event. bit 76543210 0x2c (0x4c) msb lsb ocr1b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x2b (0x4b) msb lsb ocr1c read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 bit 76543210 0x2a (0x4a) msb lsb ocr1d read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 122 8197c?avr?05/11 attiny261a/461a/861a note that, if 10-bit accuracy is used special pr ocedures must be followed when accessing the internal 10-bit output compare registers via the 8-bit avr data bus. these procedures are described in section ?accessing 10-bit registers? on page 107 . 12.12.13 timsk ? timer/counter1 interrupt mask register ? bit 7 ? ocie1d: timer/counter1 output compare interrupt enable when the ocie1d bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare matchd, interrupt is enabled. the corresponding interrupt at vector $010 is executed if a compare matchd occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 6 ? ocie1a: timer/counter1 output compare interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare matcha, interrupt is enabled. the corresponding interrupt at vector $003 is executed if a compare matcha occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 5 ? ocie1b: timer/counter1 output compare interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compare matchb, interrupt is enabled. the corresponding interrupt at vector $009 is executed if a compare matchb occurs. the compare flag in timer/counter1 is set (one) in the timer/counter interrupt flag register. ? bit 2 ? toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $004) is executed if an overflow in timer/counter1 occurs . the overflow flag (timer1) is set (one) in the timer/counter interrupt flag register - tifr. 12.12.14 tifr ? timer/counter 1 interrupt flag register ? bit 7 ? ocf1d: output compare flag 1d the ocf1d bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1d - output compare register 1d. ocf1d is cleared by hardware when executing the corresponding interrupt handling vector. alte rnatively, ocf1d is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1d, and ocf1d are set (one), the timer/counter1 d compare match interrupt is executed. ? bit 6 ? ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1a - output compare register 1a. ocf1a is cleared by hardware when executing bit 76543210 0x39 (0x59) ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 timsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x38 (0x58) ocf1d ocf1a ocf1b ocf0a ocf0b tov1 tov0 icf0 tifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 123 8197c?avr?05/11 attiny261a/461a/861a the corresponding interrupt handling vector. alternatively, ocf1a is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1a, and ocf1a are set (one), the timer/counter1 a compare match interrupt is executed. ? bit 5 ? ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between timer/counter1 and the data value in ocr1b - output compare register 1a. ocf1b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf1b is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. when the i-bit in sreg, ocie1b, and ocf1b are set (one), the timer/counter1 b compare match interrupt is executed. ? bit 2 ? tov1: timer/counter1 overflow flag in normal mode and fast pwm mode the tov1 bit is set (one) each time the counter reaches top at the same clock cycle when the counter is reset to bottom. in phase and frequency correct pwm mode the tov1 bit is set (one) each time the counter reaches bottom at the same clock cycle when zero is clocked to the counter. the bit tov1 is cleared by hardware when ex ecuting the corresponding interrupt handling vec- tor. alternatively, tov1 is cleared, after sync hronization clock cycle, by writing a logical one to the flag. when the sreg i-bit, and toie1 (tim er/counter1 overflow interrupt enable), and tov1 are set (one), the timer/counter1 overflow interrupt is executed. 12.12.15 dt1 ? timer/counter1 dead time value the dead time value register is an 8-bit read/write register. the dead time delay of all timer/counter1 channels are adjusted by the dead time value regis- ter, dt1. the register consists of two fields, dt1h[3:0] and dt1l[3:0], one for each complementary output. therefore a different dead time delay can be adjusted for the rising edge of oc1x and the rising edge of oc1x . ? bits 7:4 ? dt1h[3:0]: dead time value for oc1x output the dead time value for the oc1x output. the dead time delay is set as a number of the pres- caled timer/counter clocks. the minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. ? bits 3:0 ? dt1l[3:0]: dead time value for oc1x output the dead time value for the oc1x output. the dead time delay is set as a number of the pres- caled timer/counter clocks. the minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period multiplied by 15. bit 76543210 0x24 (0x44) dt1h3 dt1h2 dt1h1 dt1h0 dt1l3 dt1l2 dt1l1 dt1l0 dt1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 124 8197c?avr?05/11 attiny261a/461a/861a 13. usi ? universal serial interface 13.1 features ? two-wire synchronous data tr ansfer (master or slave) ? three-wire synchronous data transfer (master or slave) ? data received interrupt ? wakeup from idle mode ? in two-wire mode: wake-up from all sleep modes, including power-down mode ? two-wire start condition detect or with interr upt capability 13.2 overview the universal serial interface, or usi, provides the basic hardware resources needed for serial communication. combined with a minimum of cont rol software, the usi allows significantly higher transfer rates and uses less code space than solutions based on software only. interrupts are included to minimize the processor load. a simplified block diagram of the usi is shown in figure 13-1 for actual placement of i/o pins refer to ?pinout attiny261a/461a/861a? on page 2 . device-specific i/o register and bit loca- tions are listed in the ?register descriptions? on page 131 . figure 13-1. universal serial interface, block diagram the 8-bit usi data register (usidr) is direct ly accessible via the data bus and contains the incoming and outgoing data. the register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. the data register is a serial shift register where the most significant bit is connected to one of two output pins depending of the wire mode configura- tion. a transparent latch between the output of the data register and the output pin delays the change of data output to the opposite clock edge of the data input sampling. the serial input is always sampled from the data input (di) pin, regardless of the configuration. data bus usipf usitc usiclk usics0 usics1 usioif usioie usidc usisif usiwm0 usiwm1 usisie bit7 two-wire clock control unit do (output only) di/sda (input/open drain) usck/scl (input/open drain) 4-bit counter usidr usisr dq le usicr clock hold tim0 comp bit0 [1] 3 0 1 2 3 0 1 2 0 1 2 usidb 125 8197c?avr?05/11 attiny261a/461a/861a the 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. the data register and the counter are clocked simultaneously by the same clock source, allowing the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. note that when an external clock source is selected the counter counts both clock edges. in this case the counter counts the number of edges, and not the number of bits. the clock can be selected from three different sources: the usck pin, the timer/counter0 compare match or from software. the two-wire clock control unit can generate an interrupt when a start condition is detected on the two-wire bus. it can also generate wait states by holding the clock pin low after a start con- dition is detected, or after the counter overflows. 13.3 functional descriptions 13.3.1 three-wire mode the usi three-wire mode is compliant to the serial peripheral interface (spi) mode 0 and 1, but does not have the slave select (ss) pin functionality. however, this feature can be implemented in software if necessary. pin names used by this mode are: di, do, and usck. figure 13-2. three-wire mode operat ion, simplified diagram figure 13-2 shows two usi units operating in three-wire mode, one as master and one as slave. the two usi data register are interconnected in such way that after eight usck clocks, the data in each register are interchanged. the same clock also increments the usi?s 4-bit counter. the counter overflow (interrupt) flag, or us ioif, can therefore be used to determine when a transfer is completed. the clock is generated by the master device software by toggling the usck pin via the port register or by writing a one to the usitc bit in usicr. slave master bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 do di usck bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 do di usck portxn 126 8197c?avr?05/11 attiny261a/461a/861a figure 13-3. three-wire mode, timing diagram the three-wire mode timing is shown in figure 13 -3. at the top of the figure is a usck cycle ref- erence. one bit is shifted into the usi data register (usidr) for each of these cycles. the usck timing is shown for both external clock mo des. in external clock mode 0 (usics0 = 0), di is sampled at positive edges, and do is changed (data register is shifted by one) at negative edges. in external clock mode 1 (usics0 = 1) the opposite edges with respect to mode 0 are used. in other words, data is sampled at negati ve and output is changed at positive edges. the usi clock modes corresponds to the spi data mode 0 and 1. referring to the timing diagram ( figure 13-3 ), a bus transfer involves the following steps: 1. the slave and master devices set up their data outputs and, depending on the protocol used, enable their output drivers (mark a and b). the output is set up by writing the data to be transmitted to the usi data regi ster. the output is enabled by setting the corresponding bit in the data direction register of port a. note that there is not a pre- ferred order of points a and b in the figure, but both must be at least one half usck cycle before point c, where the data is sampled. this is in order to ensure that the data setup requirement is satisfied. the 4-bit counter is reset to zero. 2. the master software generates a clock puls e by toggling the usck line twice (c and d). the bit values on the data input (di) pins are sampled by the usi on the first edge (c), and the data output is changed on the opposite edge (d). the 4-bit counter will count both edges. 3. step 2. is repeated eight times for a complete register (byte) transfer. 4. after eight clock pulses (i.e ., 16 clock edges) the counter w ill overflow and indicate that the transfer has been completed. the data bytes transferred must now be processed before a new transfer can be initiated. the overflow interrupt will wake up the processor if it is set to idle mode. depending on the protocol used the slave device can now set its output to high impedance. 13.3.2 spi master operation example the following code demonstrates how to use the usi module as a spi master: spitransfer: sts usidr,r16 ldi r16,(1< 130 8197c?avr?05/11 attiny261a/461a/861a 3. the master set the first bit to be transferred and releases the scl line (c). the slave samples the data and shifts it into the usi data register at the positive edge of the scl clock. 4. after eight bits containing slave address and data direction (read or write) have been transferred, the slave counter overflows and the scl line is forced low (d). if the slave is not the one the master has addressed, it releases the scl line and waits for a new start condition. 5. when the slave is addressed, it holds the sda line low during the acknowledgment cycle before holding the scl line low again (i.e., the usi counter register must be set to 14 before releasing scl at (d)). depending on the r/w bit the master or slave enables its output. if the bit is set, a master read operation is in progress (i.e., the slave drives the sda line) the slave can hold the scl line low after the acknowledge (e). 6. multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (f), or a new start condition is given. if the slave is not able to receive more data it does not acknowledge the data byte it has last received. when the master does a read operation it must terminate the operation by forcing the acknowledge bit low after the last byte transmitted. 13.3.5 start condition detector the start condition detector is shown in figure 13-6 . the sda line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the scl line. the start condition detector is only enabled in two-wire mode. figure 13-6. start condition detector, logic diagram the start condition detector works asynchronous ly and can therefore wake up the processor from power-down sleep mode. however, the protocol used might have restrictions on the scl hold time. therefore, when using this feature in th is case the oscillator start-up time set by the cksel fuses (see ?clock system? on page 24 ) must also be taken into the consideration. refer to the usisif bit description on page page 132 for further details. 13.3.6 clock speed considerations maximum frequency for scl and sck is f ck / 2. this is also the maximum data transmit and receive rate in both two- and three-wire mode . in two-wire slave mode the two-wire clock con- trol unit will hold the scl low unt il the slave is ready to receive more data. this may reduce the actual data rate in two-wire mode. 13.4 alternative usi usage the flexible design of the usi allows it to be used for other tasks when serial communication is not needed. below are some examples. sda scl write( usisif) clock hold usisif dq clr dq clr 131 8197c?avr?05/11 attiny261a/461a/861a 13.4.1 half-duplex asynchronous data transfer using the usi data register in three-wire mode it is possible to implement a more compact and higher performance uart than by software, only. 13.4.2 4-bit counter the 4-bit counter can be used as a stand-alone counter with overflow interrupt. note that if the counter is clocked externally, both cl ock edges will increment the counter value. 13.4.3 12-bit timer/counter combining the 4-bit usi counter with one of the 8-bit timer/counters creates a 12-bit counter. 13.4.4 edge triggered external interrupt by setting the counter to maximum value (f) it can function as an additional external interrupt. the overflow flag and interrupt enable bit are th en used for the external interrupt. this feature is selected by the usics1 bit. 13.4.5 software interrupt the counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 13.5 register descriptions 13.5.1 usidr ? usi data register the usi data register can be accessed directly. depending on the usics[1:0] bits of the usi control register a (left) shift operation may be per- formed. the shift operation can be synchronised to an external clock edge, to a timer/counter0 compare match, or directly to software via the usiclk bit. if a serial clock occurs at the same cycle the register is written, the register will c ontain the value written a nd no shift is performed. note that even when no wire mode is selected (usiwm[1:0] = 0) both the external data input (di/sda) and the external clock input (usck/scl) can still be used by the usi data register. the output pin (do or sda, depending on the wire mode) is connected via the output latch to the most significant bit (bit 7) of the usi data register. the output latch ensures that data input is sampled and data output is changed on opposite clock edges. the latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (usics1 = 1) and constantly open when an internal clock source is used (usics1 = 0). the out- put will be changed immedi ately when a new msb is written as long as the latch is open. note that the data direction register bit corresponding to the output pin must be set to one in order to enable data output from the usi data register. bit 7 6 5 4 3 2 1 0 0x0f (0x2f) msb lsb usidr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 132 8197c?avr?05/11 attiny261a/461a/861a 13.5.2 usibr ? usi buffer register the content of the serial register is loaded to the usi buffer register when the trasfer is com- pleted, and instead of accessing the usi data register (the serial register) the usi data buffer can be accessed when the cpu reads the receiv ed data. this gives the cpu time to handle other program tasks too as the controlling of the usi is not so timing critical. the usi flags as set same as when reading the usidr register. 13.5.3 usisr ? usi status register the status register contains interrupt flags, line status flags and the counter value. ? bit 7 ? usisif: start condition interrupt flag when two-wire mode is selected, the usisif flag is set (to one) when a start condition is detected. when output disable mode or three-wire mode is selected and (usicsx = 0b11 & usiclk = 0) or (usics = 0b10 & usiclk = 0), any edge on the sck pin sets the flag. an interrupt will be generated when the flag is set while th e usisie bit in usicr and the global interrupt enable flag are set. the flag will only be cleared by writing a logical one to the usisif bit. clearing this bit will release the start de tection hold of uscl in two-wire mode. a start condition interr upt will wakeup the processor from all sleep modes. ? bit 6 ? usioif: counter overflow interrupt flag this flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). an interrupt will be generate d when the flag is set while the usioie bit in usicr and the global interrupt enable flag ar e set. the flag will only be cleared if a one is written to the usioif bit. clearing this bit will release the counter overfl ow hold of scl in two-wire mode. a counter overflow interrup t will wakeup the processor from idle sleep mode. ? bit 5 ? usipf: stop condition flag when two-wire mode is selected, the usipf flag is set (one) when a stop condition is detected. the flag is cleared by writing a one to this bit. note that this is not an interrupt flag. this signal is useful when implementing two-wire bus master arbitration. ? bit 4 ? usidc: data output collision this bit is logical one when bit 7 in the usi data register differs from the physical pin value. the flag is only valid when two-wire mode is used. this signal is useful when implementing two- wire bus master arbitration. ? bits 3:0 ? usicnt[3:0]: counter value these bits reflect the current 4-bit counter value. the 4-bit counter value can directly be read or written by the cpu. bit 7 6 5 4 3 2 1 0 0x10 (0x30) msb lsb usibr read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 0x0e (0x2e) usisif usioif usipf usidc usi cnt3 usicnt2 usicnt1 usicnt0 usisr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 133 8197c?avr?05/11 attiny261a/461a/861a the 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a timer/counter0 compare match, or by software using usiclk or usitc strobe bits. the clock source depends of the setting of the usics[1:0] bits. for external clock operation a special feature is added that allows the clock to be generated by writing to the usitc strobe bit. this feature is enabled by write a one to the usiclk bit while setting an external clock source (usics1 = 1). note that even when no wire mode is selected (usiwm[1:0] = 0) the external clock input (usck/scl) are can still be used by the counter. 13.5.4 usicr ? usi control register the control register includes interrupt enable control, wire mode setting, clock select setting, and clock strobe. ? bit 7 ? usisie: start condition interrupt enable setting this bit to one enables the start condition detector interrupt. if there is a pending inter- rupt when the usisie and the globa l interrupt enable flag is set to one, this will immediately be executed. refer to the usisif bit description on page page 132 for further details. ? bit 6 ? usioie: counter overflow interrupt enable setting this bit to one enables the counter overflow interrupt. if there is a pending interrupt when the usioie and the global interrupt enable flag is set to one, this will immediately be executed. refer to the usioif bit description on page page 132 for further details. ? bit 5:4 ? usiwm[1:0]: wire mode these bits set the type of wire mode to be used, as shown in table 13-1 on page 133 . basically, only the function of the outputs are affected by these bits. data and clock inputs are not affected by t he mode selected and will always have th e same function. the counter and usi data register can therefore be clocked exte rnally, and data input sampled, even when outputs are disabled. bit 7 6 5 4 3 2 1 0 0x0d (0x2d) usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc usicr read/write r/w r/w r/w r/w r/w r/w w w initial value 0 0 0 0 0 0 0 0 table 13-1. relationship between usiw m[1:0] and usi operation usiwm1 usiwm0 description 00 outputs, clock hold, and start detector disabled. port pins operate as normal. 01 three-wire mode. uses do, di, and usck pins. the data output (do) pin overrides the corresponding bit in the porta register. however, the corresponding ddra bit still controls the data direction. when the port pin is set as input the pi n pull-up is controlled by the porta bit. the data input (di) and serial clock (usck) pins do not affect the normal port operation. when operating as master, clock pulses are software generated by toggling the porta register, while the da ta direction is set to output. the usitc bit in the usicr register can be used for this purpose. 134 8197c?avr?05/11 attiny261a/461a/861a note: 1. the di and usck pins are renamed to serial data (sda) and serial clock (scl) respectively to avoid confusion between the modes of operation. ? bits 3:2 ? usics[1:0]: clock source select these bits set the clock source for the usi data registerr and counter. the data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (di/sda) when using external clock source (usck/scl). when software strobe or timer/counter0 compare match clock option is selected, the output latch is transparent and therefore the output is changed immediately. cl earing the usics[1:0] bits enables software strobe option. when using this option, writing a one to the usiclk bit clocks both the usi data register and the counter. for external clock sour ce (usics1 = 1), the usiclk bit is no longer used as a strobe, but selects between external clocking and software clocking by the usitc strobe bit. table 13-2 on page 134 shows the relationship between the usics[1:0] and usiclk setting and clock source used for the usi data register and the 4-bit counter. 10 two-wire mode. uses sda (di) and scl (usck) pins (1) . the serial data (sda) and the serial clock (scl) pins are bi-directional and use open-collector output drives. the out put drivers are enabled by setting the corresponding bit for sda and scl in the ddra register. when the output driver is enabled for the sda pin, the output driver will force the line sda low if the output of the usi data register or the corresponding bit in the porta register is zero. otherwise, the sda line will not be driven (i.e., it is released). when the scl pin output driver is enabled the scl line will be forced low if the corresponding bit in the porta register is zero, or by the start detector. otherwise the scl line will not be driven. the scl line is held low when a start de tector detects a start condition and the output is enabled. clearing the start c ondition flag (usisif) releases the line. the sda and scl pin inputs is not affected by enabling this mode. pull-ups on the sda and scl port pin are disabled in two-wire mode. 11 two-wire mode. uses sda and scl pins. same operation as in two-wire mode abo ve, except that the scl line is also held low when a counter overflow occurs, and until the counter overflow flag (usioif) is cleared. table 13-2. relations between the usics[1:0] and usiclk setting usics1 usics0 usiclk usi data register clock source 4-bit counter clock source 0 0 0 no clock no clock 001 software clock strobe (usiclk) software clock strobe (usiclk) 01x timer/counter0 compare match timer/counter0 compare match 1 0 0 external, positive edge external, both edges table 13-1. relationship between usiwm[1:0] and usi operation (continued) usiwm1 usiwm0 description 135 8197c?avr?05/11 attiny261a/461a/861a ? bit 1 ? usiclk: clock strobe writing a one to this bit location strobes the usi data register to shift one step and the counter to increment by one, provided that the usics[1:0] bits are set to zero and by doing so the soft- ware clock strobe option is selected. the output will change immediately when the clock strobe is executed, i.e., in the same instruction cycle. the value shifted into the usi data register is sampled the previous in struction cycle. the bit will be read as zero. when an external clock source is selected (usics1 = 1), the usiclk function is changed from a clock strobe to a clock select register. setting the usiclk bit in this case will select the usitc strobe bit as clock sour ce for the 4-bit counter (see table 13-2 ). ? bit 0 ? usitc: toggle clock port pin writing a one to this bit location toggles the usck/s cl value either from 0 to 1, or from 1 to 0. the toggling is independent of the setting in the data direction register, but if the port value is to be shown on the pin the ddb2 must be set as output (to one). this feature allows easy clock generation when implementi ng master devices. the bit will be read as zero. when an external clock source is selected (usics 1 = 1) and the usiclk bit is set to one, writ- ing to the usitc strobe bit will directly clock th e 4-bit counter. this allows an early detection of when the transfer is done when operating as a master device. 13.5.5 usipp ? usi pin position ? bits 7:1 ? res: reserved bits these bits are reserved and will always read as zero. ? bit 0 ? usipos: usi pin position setting this bit to one changes the usi pin position. as default pins pb[2:0] are used for the usi pin functions, but when writing this bit to one th e usipos bit is set the usi pin functions are on pins pa[2:0]. 1 1 0 external, negative edge external, both edges 1 0 1 external, positive edge so ftware clock strobe (usitc) 1 1 1 external, negative edge software clock strobe (usitc) table 13-2. relations between the usics[1:0] and usiclk setting (continued) usics1 usics0 usiclk usi data register clock source 4-bit counter clock source bit 76543210 0x11 (0x31) ???????usiposusipp read/writerrrrrrrr/w initial value00000000 136 8197c?avr?05/11 attiny261a/461a/861a 14. ac ? analog comparator the analog comparator compares the input values on the selectable positive pin (ain0, ain1 or ain2) and selectable negative pin (ain0, ain1 or ain2). when the voltage on the positive pin is higher than the voltage on the negative pin, the analog comparator output, aco, is set. the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output ri se, fall or toggle. a block diagram of the com- parator and its surrounding logic is shown in figure 14-1 . figure 14-1. analog comparator block diagram notes: 1. see table 14-1 on page 136 . see figure 1-1 on page 2 and table 10-3 on page 62 for analog comparator pin placement. 14.1 analog comparator multiplexed input when the analog to digital converter (adc) is configurated as single ended input channel, it is possible to select any of the adc[10:0] pins to replace the negative input to the analog compar- ator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (ade n in adcsra is zero), mux[5:0] in admux select the input pin to replace the negative input to the analog comparator, as shown in table 14-1 . if acme is cleared or aden is set, either ain0, ain1 or ain2 is applied to the negative input to the analog comparator. acbg bandgap referen ce i n terru pt select analog com pa rator irq aci acie vcc acd aco acis1 + _ acis0 adc multiplexer output acme aden (1) mux ain0 ain1 ain2 acm[2:0] hsel hlev table 14-1. analog comparator multiplexed input acme aden mux[5:0] acm[2:0] positive input negative input 0 x xxxxxx 000 ain0 ain1 0 x xxxxxx 001 ain0 ain2 0 x xxxxxx 010 ain1 ain0 0 x xxxxxx 011 ain1 ain2 137 8197c?avr?05/11 attiny261a/461a/861a 0 x xxxxxx 100 ain2 ain0 0 x xxxxxx 101,110,111 ain2 ain1 1 1 xxxxxx 000 ain0 ain1 1 0 000000 000 ain0 adc0 1 0 000000 01x ain1 adc0 1 0 000000 1xx ain2 adc0 1 0 000001 000 ain0 adc1 1 0 000001 01x ain1 adc1 1 0 000001 1xx ain2 adc1 1 0 000010 000 ain0 adc2 1 0 000010 01x ain1 adc2 1 0 000010 1xx ain2 adc2 1 0 000011 000 ain0 adc3 1 0 000011 01x ain1 adc3 1 0 000011 1xx ain2 adc3 1 0 000100 000 ain0 adc4 1 0 000100 01x ain1 adc4 1 0 000100 1xx ain2 adc4 1 0 000101 000 ain0 adc5 1 0 000101 01x ain1 adc5 1 0 000101 1xx ain2 adc5 1 0 000110 000 ain0 adc6 1 0 000110 01x ain1 adc6 1 0 000110 1xx ain2 adc6 1 0 000111 000 ain0 adc7 1 0 000111 01x ain1 adc7 1 0 000111 1xx ain2 adc7 1 0 001000 000 ain0 adc8 1 0 001000 01x ain1 adc8 1 0 001000 1xx ain2 adc8 1 0 001001 000 ain0 adc9 1 0 001001 01x ain1 adc9 1 0 001001 1xx ain2 adc9 1 0 001010 000 ain0 adc10 1 0 001010 01x ain1 adc10 1 0 001010 1xx ain2 adc10 table 14-1. analog comparator multiplexed input (continued) acme aden mux[5:0] acm[2:0] positive input negative input 138 8197c?avr?05/11 attiny261a/461a/861a 14.2 register description 14.2.1 acsra ? analog comparator control and status register a ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to turn off the analog comparator, thus reducing power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be dis- abled by clearing the acie bit in acsra. ot herwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set an internal 1.1v referenc e voltage replaces the positive input to the analog comparator. the selection of the internal voltage reference is done by writing the refs[2:0] bits in adcsrb and admux registers. when this bi t is cleared, ain0, ain1 or ain2 depending on the acm[2:0] bits is applied to the positive input of the analog comparator. ? bit 5 ? aco: analog comparator output enables output of analog comparator. the output of the analog comparator is synchronized and then directly connected to aco. the synchroniz ation introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bit in the status register is set, the analog com- parator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed descrip- tion of this bit, see table 14-1 on page 136 . bit 76543210 0x08 (0x28) acd acbg aco aci acie acme acis1 acis0 acsra read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000 139 8197c?avr?05/11 attiny261a/461a/861a ? bits 1:0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 14-2 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. 14.2.2 acsrb ? analog comparator control and status register b ? bit 7 ? hsel: hysteresis select when this bit is written logic one, the hysteresis of the analog comparator is switched on. the hysteresis level is se lected by the hlev bit. ? bit 6 ? hlev: hysteresis level when the hysteresis is enabled by the hsel bit, the hysteresis level, hlev, bit selects the hys- teresis level that is either 20mv (hlev=0) or 50mv (hlev=1). ? bits 2:0 ? acm[2:0]: analog comparator multiplexer the analog comparator multiplexer bits select th e positive and negative input pins of the analog comparator. the different settings are shown in table 14-1 . 14.2.3 didr0 ? digital in put disable register 0 ? bits 7:4, 2:0 ? adc6d:adc0d: adc[6:0] digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc[6:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ? bit 3 ? arefd: aref digital input disable when this bit is written logic on e, the digital input buffer on the aref pin is disabled. the corre- sponding pin register bit will alwa ys read as zero when this bit is set. when an analog signal is table 14-2. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 76543210 0x09 (0x29) hsel hlev ? ? ? acm2 acm1 acm0 acsrb read/write r/w r/w r r r r/w r/w r/w initial value00n/a00000 bit 76543210 0x01 (0x21) adc6d adc5d adc4d adc3d arefd adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 140 8197c?avr?05/11 attiny261a/461a/861a applied to the aref pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 14.2.4 didr1 ? digital in put disable register 1 ? bits 7:4 ? adc10d:adc7d: adc[10:7] digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc[10:7] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. bit 76543210 0x02 (0x22) adc10d adc9d adc8d adc7d ? ? ? ?didr1 read/write r/w r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 141 8197c?avr?05/11 attiny261a/461a/861a 15. adc ? analog to digital converter 15.1 features ? 10-bit resolution ? 1.0 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13 s conversion time ? 15 ksps at maximum resolution ? 11 multiplexed single ended input channels ? 16 differential input pairs ? 15 differential input pa irs with selectable gain ? temperature sensor input channel ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 1.1v / 2.56v adc voltage reference ? free running or single conversion mode ? adc start conversion by auto tr iggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode no ise cancele ? unipolar / bipolar input mode ? input polarity reversal mode 15.2 overview a 10-bit, successive approximation, analog to digital converter (adc) is connected to a 11- channel analog multiplexer, which allows 16 diffe rential voltage input combinations and 11 sin- gle-ended voltage inputs constructed from the pins pa[7:0] or pb[7:4]. the differential input is equipped with a programmable gain stage, providing amplification steps of 1x, 8x, 20x or 32x on the differential input voltage before the a/d conversion. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 15-1 on page 142 . internal reference voltages of nominally 1.1v or 2.56v are provided on-chip. the internal refer- ance voltage of 2.56v, can optionally be externa lly decoupled at the aref (pa3) pin by a capacitor, for better noise performance. alternatively, v cc can be used as reference voltage for single ended channels. there is also an option to use an external voltage reference and turn-off the internal voltage reference. these options are selected using the refs[2:0] bits of the adc- srb and admux registers. 142 8197c?avr?05/11 attiny261a/461a/861a figure 15-1. analog to digital converter block schematic 15.3 operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on v cc , the voltage on the aref pin or an internal 1.1v / 2.56v voltage reference. the voltage reference for the adc may be selected by writing to the refs[2:0] bits in adcsrb and admux registers. the vcc supply, the aref pin or an internal 1.1v / 2.56v voltage refer- ence may be selected as the adc voltage reference. optionally the internal 1.1v / 2.56v voltage adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register a (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator mux decoder mux4 adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output gain amplifier internal 1.1v reference prescaler single ended / differential selection agnd pos. input mux neg. input mux adc10 adc9 adc8 vcc aref temperature sensor internal 2.56/1.1v reference mux adc ctrl. & status register b (adcsrb) refs2 gsel mux5 143 8197c?avr?05/11 attiny261a/461a/861a reference may be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differential gain are se lected by writing to the mux[5:0] bits in admux. any of the 11 adc input pins adc[10:0] can be selected as single ended inputs to the adc. the positive and negative inputs to the differential gain amplifier are described in table 15-5 . if differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input pair by the selected gain factor, 1x, 8x, 20x or 32x, according to the setting of the mux[5:0] bits in admux and the gsel bit in adcsrb. this amplified value then becomes the analog input to the adc. if single ended channels are used, the gain amplifier is bypassed altogether. if the same adc input pin is selected as both the positive and negative input to the differential gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. this figure can be subtracted from subsequent conver- sions with the same gain setting to reduce offset error to below 1 lsw. the on-chip temperature sensor is selected by writing the code ?111111? to the mux[5:0] bits in admux register when the adc11 chan nel is used as an adc input. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been r ead, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between r eading of adch and ad cl, the in terrupt will trigger even if the result is lost. 15.4 starting a conversion a single conversion is started by writing a l ogical one to the adc start conversion bit, adsc. this bit stays high as long as the conversi on is in progress and will be cleared by hardware when the conversion is completed. if a different data channel is selected while a conversion is in progress, the adc will finish the current conv ersion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if the trigger signal still is set when the conversion completes, a new 144 8197c?avr?05/11 attiny261a/461a/861a conversion will not be star ted. if another positive edge occurs on the trigger si gnal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. figure 15-2. adc auto trigger logic using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 15.5 prescaling and conversion timing by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. figure 15-3. adc prescaler adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 145 8197c?avr?05/11 attiny261a/461a/861a the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100 khz. the presca ling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as lo ng as the aden bit is set, and is continuously reset when aden is low. see figure 15-3 . when initiating a single ended conversion by se tting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry, as shown in figure 15-4 below. figure 15-4. adc timing diagram, first conver sion (single conversion mode) the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of an first conversion. see figure 15-5 . when a conversion is complete, th e result is written to the adc da ta registers, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the fi rst rising adc clock edge. figure 15-5. adc timing diagram, single conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 146 8197c?avr?05/11 attiny261a/461a/861a when auto triggering is used, the prescale r is reset when the trig ger event occurs. see figure 15-6 . this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clo ck cycles after the rising edge on the trigger source signal. three additional cpu clock cycles are used for synchronization logic. figure 15-6. adc timing diagram, auto triggered conversion in free running mode (see figure 15-7 ), a new conversion will be st arted immediately after the conversion completes, wh ile adsc remains high. figure 15-7. adc timing diagram, free running conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 147 8197c?avr?05/11 attiny261a/461a/861a for a summary of conversion times, see table 15-1 . 15.6 changing channel or reference selection the mux[5:0] and refs[2:0] bits in the adcsrb and admux registers are single buffered through a temporary register to which the cpu has random access. this ensures that the chan- nels and reference selection only takes place at a safe point during the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conver- sion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion com- pletes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is t hus advised not to write new channel or reference selection values to admux until one a dc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: ? when adate or aden is cleared. ? during conversion, minimum one adc clock cycle after the trigger event. ? after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. 15.6.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel table 15-1. adc conversion time condition sample & hold (cycles from start of conversion ) total conversion time (cycles) first conversion 13.5 25 normal conversions 1.5 13 auto triggered conversions 2 13.5 148 8197c?avr?05/11 attiny261a/461a/861a selection. since the next conver sion has already started automati cally, the next result will reflect the previous channel selection. subsequent conversions will refl ect the new channel selection. 15.6.2 adc voltage reference the conversion range of the adc is defined by the voltage reference (v ref ). single ended chan- nels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either v cc , or internal 1.1v / 2.56v voltage reference, or exte rnal aref pin. the firs t conversion result after switching voltage reference source may be inaccu rate, and the user is advised to discard this result. 15.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode. this reduces noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: ? make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. ? enter adc noise reduction mode (or idle mode ). the adc will start a conversion once the cpu has been halted. ? if no other interrupts occur be fore the adc conversion comple tes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is complete, it will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in active m ode until a new sleep command is executed. note that the adc will not automatically be turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. 15.8 analog input circuitry the analog input circuitry for sing le ended channels is illustrated in figure 15-8 an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the adc. when the channel is selected, the source must drive the s/h capacitor through the series resistance (combined resistance in the input path). 149 8197c?avr?05/11 attiny261a/461a/861a figure 15-8. analog input circuitry the capacitor in figure 15-8 depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. the value given is worst case. the adc is optimized for analog signals wit h an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long the source needs to charge the s/h capacitor, with can vary widely. the user is recommended to minmimize the charge transfer time by using low impedant sources, on ly, with slowly varying signals. signal components higher than the nyquist frequency (f adc /2) should not be present to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. 15.9 noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. when conversion accuracy is critical, the noise level can be reduced by applying the following techniques: ? keep analog signal paths as short as possible. ? make sure analog tracks run over the analog ground plane. ? keep analog tracks well away from high-speed switching digital tracks. ? if any port pin is used as a digital output, it mustn?t switch while a conversion is in progress. ? place bypass capacitors as close to v cc and gnd pins as possible. where high adc accuracy is required it is recommended to use adc noise reduction mode, as described in section 15.7 on page 148 . this is especially the case when system clock frequency is above 1 mhz, or when the adc is used for reading the internal temperature sensor, as described in section 15.12 on page 153 . a good system design with properly placed, external bypass capacitors does reduce the need for using adc noise reduction mode 15.10 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: adcn i ih 1..100 k c s/h = 14 pf v cc /2 i il 150 8197c?avr?05/11 attiny261a/461a/861a ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 15-9. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 15-10. gain error output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 151 8197c?avr?05/11 attiny261a/461a/861a ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 15-11. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 15-12. differential non-linearity (dnl) output code v ref input voltage ideal adc actual adc inl output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb 152 8197c?avr?05/11 attiny261a/461a/861a ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 15.11 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch) . the form of the conversion result depends on the type of the conversio as there are three types of conversions: single ended c onversion, unipolar differential conversion and bipolar differential conversion. 15.11.1 single ended conversion for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 15-4 on page 156 and table 15-5 on page 157 ). 0x000 represents analog ground, and 0x3ff represents the selected voltage reference minus one lsb. the result is presented in one- sided form, from 0x3ff to 0x000. 15.11.2 unipolar differential conversion if differential channels and an unipolar input mode are used, the result is where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference (see table 15-4 on page 156 and table 15-5 on page 157 ). the voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. the result is presented in one-sided form, from 0x000 (0d) to 0x3ff (+1023d). the gain is either 1x, 8x, 20x or 32x. 15.11.3 bipolar differential conversion as default the adc converter operates in the unipolar input mode, but the bipolar input mode can be selected by writting the bin bit in the adcsrb to one. in the bipolar input mode two- sided voltage differences are allowed and thus the voltage on the negative input pin can also be larger than the voltage on the positive input pin. if differential channels and a bipolar input mode are used, the result is adc v in 1024 ? v ref -------------------------- = adc v pos v neg ? () 1024 ? v ref ------------------------------------------------------- - gain ? = 153 8197c?avr?05/11 attiny261a/461a/861a where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, and v ref the selected voltage reference. the result is presented in two?s complement form, from 0x200 (-512d) through 0x000 (+0d) to 0x1ff (+511d). the gain is either 1x, 8x, 20x or 32x. however, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses one bit of the converter dynamic range. then, if the user wants to perform the conversion with the maximum dynamic range, the user can perfor m a quick polarity check of the result and use the unipolar differential conversion with selectabl e differential input pair. when the polarity check is performed, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is negative, and if this bi t is zero, the result is positive. 15.12 temperature measurement the temperature measurement is based on an on-ch ip temperature sensor that is coupled to a single ended adc11 channel. selecting the adc11 channel by writing the mux[5:0] bits in admux register to ?111111? enables the temperat ure sensor. the internal 1.1v voltage refer- ence must also be selected for the adc voltage reference source in the temperature sensor measurement. when the temperature sensor is en abled, the adc converter can be used in sin- gle conversion mode to measure the voltage over the temperature sensor. the measured voltage has a linear relationship to the temperature as described in table 15-2 the sensitivity is approximately 1 lsb / c and the accuracy depends on the method of user cal- ibration. typically, the measurement accuracy after a single temperature calibration is 10 c, assuming calibration at room temperature. better accuracies are achieved by using two temperature points for calibration. the values described in table 15-2 are typical values. however, due to process variation the temperature sensor output voltage varies from one chip to another. to be capable of achieving more accurate results the temperature measurement can be calibrated in the application soft- ware. the sofware calibration can be done using the formula: t = k * [(adch << 8) | adcl] + t os where adch and adcl are the adc data registers, k is the fixed slope coefficient and t os is the temperature sensor offset. typically, k is very close to 1.0 and in single-point calibration the coefficient may be omitted. where higher accura cy is required the slope coefficient should be evaluated based on measurements at two temperatures. adc v pos v neg ? () 512 ? v ref ---------------------------------------------------- - gain ? = table 15-2. temperature vs. sensor output voltage (typical case) temperature -40 c+25 c+85 c adc 230 lsb 300 lsb 370 lsb 154 8197c?avr?05/11 attiny261a/461a/861a 15.13 register description 15.13.1 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writi ng it to zero, the adc is turned off. turning the adc off while a conversion is in prog ress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the norma l 13. this first conversi on performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. when the co nversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to on e, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if th e adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corres ponding interrupt handling vector. alternatively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete inter- rupt is activated. ? bits 2:0 ? adps[2:0]: adc prescaler select bits these bits determine the division factor betwee n the system clock frequency and the input clock to the adc. bit 76543210 0x06 (0x26) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 15-3. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 155 8197c?avr?05/11 attiny261a/461a/861a 15.13.2 adcl and adch ? the adc data register 15.13.2.1 adlar = 0 15.13.2.2 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated unt il adch is read. consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. ? adc[9:0]: adc conversion result these bits represent the result from the conversion, as detailed in ?adc conversion result? on page 152 . 15.13.3 admux ? adc multiplexer selection register 100 16 101 32 110 64 1 1 1 128 table 15-3. adc prescaler selections (continued) adps2 adps1 adps0 division factor bit 151413121110 9 8 0x05 (0x25) ?????? adc9 adc8 adch 0x04 (0x24) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 0x05 (0x25) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch 0x04 (0x24) adc1 adc0 ??????adcl 76543210 read/write rrrrrrrr rrrrrrrr initial value00000000 00000000 bit 76543210 0x07 (0x27) refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 156 8197c?avr?05/11 attiny261a/461a/861a ? bits 7:6 ? refs[1:0]: voltage reference selection bits these bits together with the refs2 bit from the adc control and status register b (adcsrb) select the voltage reference for the adc, as shown in table 15-4 . if these bits are changed during a conversion, the change will not go in effect until this conver- sion is complete (adif in adcsr is set). also note, that when these bits are changed, the next conversion will take 25 adc clock cycles. special care should be taken when changing differential channels. once a differential channel has been selected the input sta ge may take a while to stabilize. it is therefor e recommended to force the adc to perform a long conversion when changing multiplexer or voltage reference set- tings. this can be done by first turning off t he adc, then changing reference settings and then turn on the adc. alternatively, the first conv ersion results after changing reference settings should be discarded. it is not recommended to use an external aref higher than (v cc - 1v) for channels with differ- ential gain, as this will affect adc accuracy. internal voltage reference options may not be used if an external voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affect t he adc data register immediately, regardless of any ongoing conver- sions. for a comple te description of this bit, see ?adcl and adch ? the adc data register? on page 155 . ? bits 4:0 ? mux[4:0]: analog channel and gain selection bits these bits and the mux5 bit from the adc control and status register b (adcsrb) select which combination of analog inputs are connected to the adc. in case of differential input, gain selection is also made with these bits. selecting the same pin as both inputs to the differential table 15-4. voltage reference selections for adc refs2 refs1 refs0 voltage reference selection x00 v cc used as voltage reference, disconnected from aref x01 external voltage reference at aref pin, internal voltage reference turned off 0 1 0 internal 1.1v voltage reference 011reserved 110 internal 2.56v voltage reference ( v cc > 3.0v), without external bypass capacitor, disconnected from aref 111 internal 2.56v voltage reference ( v cc > 3.0v), with external bypass capacitor at aref pin. note: external voltages may not be applied to the pin! 157 8197c?avr?05/11 attiny261a/461a/861a gain stage enables offset measurements. sele cting the single-ended channel adc11 enables the temperature sensor. refer to table 15-5 for details. table 15-5. input channel selections mux[5:0] single-ended input differential input gain positive negative 000000 adc0 (pa0) na na na 000001 adc1 (pa1) 000010 adc2 (pa2) 000011 adc3 (pa4) 000100 adc4 (pa5) 000101 adc5 (pa6) 000110 adc6 (pa7) 000111 adc7 (pb4) 001000 adc8 (pb5) 001001 adc9 (pb6) 001010 adc10 (pb7) 001011 na adc0 (pa0) adc1 (pa1) 20x 001100 adc0 (pa0) adc1 (pa1) 1x 001101 adc1 (pa1) adc1 (pa1) 20x 001110 adc2 (pa2) adc1 (pa1) 20x 001111 adc2 (pa2) adc1 (pa1) 1x 010000 n/a adc2 (pa2) adc3 (pa4) 1x 010001 adc3 (pa4) adc3 (pa4) 20x 010010 adc4 (pa5) adc3 (pa4) 20x 010011 adc4 (pa5) adc3 (pa4) 1x 010100 na adc4 (pa5) adc5 (pa6) 20x 010101 adc4 (pa5) adc5 (pa6) 1x 010110 adc5 (pa6) adc5 (pa6) 20x 010111 adc6 (pa7) adc5 (pa6) 20x 011000 adc6 (pa7) adc5 (pa6) 1x 011001 na adc8 (pb5) adc9 (pb6) 20x 011010 adc8 (pb5) adc9 (pb6) 1x 011011 adc9 (pb6) adc9 (pb6) 20x 011100 adc10 (pb7) adc9 (pb6) 20x 011101 adc10 (pb7) adc9 (pb6) 1x 011110 (1) 1.1v n/a n/a n/a 011111 0v 158 8197c?avr?05/11 attiny261a/461a/861a note: 1. after switching to internal voltage referenc e the adc requires a settling time of 1ms before measurements are stable. conversions starting before this may not be reliable. the adc must be enabled during the settling time. 2. temperature sensor 100000 n/a adc0(pa0) adc1(pa1) 20x/32x 100001 adc0(pa0) adc1(pa1) 1x/8x 100010 adc1(pa1 adc0(pa0) 20x/32x 100011 adc1(pa1) adc0(pa0) 1x/8x 100100 n/a adc1(pa1) adc2(pa2) 20x/32x 100101 adc1(pa1) adc2(pa2) 1x/8x 100110 adc2(pa2 adc1(pa1) 20x/32x 100111 adc2(pa2) adc1(pa1) 1x/8x 101000 n/a adc2(pa2) adc0(pa0) 20x/32x 101001 adc2(pa2) adc0(pa0) 1x/8x 101010 adc0(pa0) adc2(pa2) 20x/32x 101011 adc0(pa0) adc2(pa2) 1x/8x 101100 n/a adc4(pa5) adc5(pa6) 20x/32x 101101 adc4(pa5) adc5(pa6) 1x/8x 101110 adc5(pa6) adc4(pa5) 20x/32x 101111 adc5(pa6) adc4(pa5) 1x/8x 110000 n/a adc5(pa6) adc6(pa7) 20x/32x 110001 adc5(pa6) adc6(pa7) 1x/8x 110010 adc6(pa7) adc5(pa6) 20x/32x 110011 adc6(pa7) adc5(pa6) 1x/8x 110100 n/a adc6(pa7) adc4(pa5) 20x/32x 110101 adc6(pa7) adc4(pa5) 1x/8x 110110 adc4(pa5) adc6(pa7) 20x/32x 110111 adc4(pa5) adc6(pa7) 1x/8x 111000 n/a adc0(pa0) adc0(pa0) 20x/32x 111001 adc0(pa0) adc0(pa0) 1x/8x 111010 adc1(pa1) adc1(pa1) 20x/32x 111011 adc2(pa2) adc2(pa2) 20x/32x 111100 n/a adc4(pa5) adc4(pa5) 20x/32x 111101 adc5(pa6) adc5(pa6) 20x/32x 111110 adc6(pa7) adc6(pa7) 20x/32x 111111 adc11 (2) n/a n/a n/a table 15-5. input channel selections (continued) mux[5:0] single-ended input differential input gain positive negative 159 8197c?avr?05/11 attiny261a/461a/861a if these bits are changed during a conversion, the change will not go into effect until this conver- sion is complete (adif in adcsra is set). 15.13.4 adcsrb ? adc control and status register b ? bit 7 ? bin: bipolar input mode the gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the bin bit in the adcsrb register. in the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. otherwise the result is saturated to the voltage reference. in the bipolar mode two-sided conversions are supported and the result is represented in the two?s complement form. in the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. ? bit 6 ? gsel: gain select the gain select bit selects the 32x gain instead of the 20x gain and the 8x gain instead of the 1x gain when the gain select bit is written to one. ? bit 5 ? res: reserved bit this bit is reserved and will always read zero. ? bit 4 ? refs2: reference selection bit these bit selects either the voltage reference of 1.1 v or 2.56 v for the adc, as shown in table 15-4 . if active channels are used, using avcc or an external aref higher than (avcc - 1v) is not recommended, as this will affect adc accuracy. ? bit 3 ? mux5: analog channel and gain selection bit 5 the mux5 bit is the msb of the analog channel and gain selection bits. refer to table 15-5 for details. if this bit is changed during a conver sion, the change will not go into effect until this conversion is complete (adif in adcsra is set). ? bits 2:0 ? adts[2:0]: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts[2:0] settings will have no effect. a conver- sion will be triggered by the rising edge of the selected in terrupt flag. note th at switching from a trigger source that is cleared to a trigger sour ce that is set, will generate a positive edge on the bit 7 6543210 0x03 (0x23) bin gsel ? refs2 mux5 adts2 adts1 adts0 adcsrb read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 160 8197c?avr?05/11 attiny261a/461a/861a trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if t he adc interrupt flag is set . 15.13.5 didr0 ? digital input disable register 0 ? bits 7:4, 2:0 ? adc6d:adc0d: adc[6:0] digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc[6:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ? bit 3 ? arefd: aref digital input disable when this bit is written logic on e, the digital input buffer on the aref pin is disabled. the corre- sponding pin register bit will alwa ys read as zero when this bit is set. when an analog signal is applied to the aref pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 15.13.6 didr1 ? digital input disable register 1 ? bits 7:4 ? adc10d:adc7d: adc[10:7] digital input disable when this bit is written logic one, the digita l input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc[10:7] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 15-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter0 compare match b 1 1 0 timer/counter1 overflow 1 1 1 watchdog interrupt request bit 76543210 0x01 (0x21) adc6d adc5d adc4d adc3d arefd adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x02 (0x22) adc10d adc9d adc8d adc7d ? ? ? ?didr1 read/write r/w r/w r/w r/w r r r r initial value 0 0 0 0 0 0 0 0 161 8197c?avr?05/11 attiny261a/461a/861a 16. debugwire on-chip debug system 16.1 features ? complete program flow control ? emulates all on-chip functions, both digital and an alog , except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of prog ram break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 16.2 overview the debugwire on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 16.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the commu- nication gateway between target and emulator. figure 16-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. figure 16-1. the debugwire setup dw gnd dw(reset) vcc 1.8 - 5.5v 162 8197c?avr?05/11 attiny261a/461a/861a when designing a system where debugwire will be used, the following must be observed: ? pull-up resistor on the dw/(reset) line must be in the ra nge of 10k to 20 k . however, the pull-up resistor is optional. ? connecting the reset pin directly to v cc will not work. ? capacitors inserted on the reset pin must be disconnected when using debugwire. ? all external reset sources must be disconnected. 16.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instruction in the program memo ry. the instruc- tion replaced by the break instru ction will be stored. when program execution is continued, the stored instruction will be execut ed before continuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio th rough the debugwire inte rface. the use of brea k points will therefore reduce the falsh data retention. devices used for debugging purposes should not be shipped to end customers. 16.5 limitations of debugwire the debugwire communication pin (dw) is physica lly located on the same pin as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately emulates all i/ o functions when running at full speed, i.e., when the program in the cpu is running. when the cpu is stopped, care must be taken while accessing some of the i/o registers via the debugger (avr studio). see the debugwire docu- mentation for detailed description of the limitations. the debugwire interface is asynchronous, whic h means that the debugger needs to synchro- nize to the system clock. if the system clock is changed by software (e.g . by writing clkps bits) communication via debugwire may fail. also, clock frequencies below 100 khz may cause communication problems. a programmed dwen fuse enable s some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 16.6 register description the following section describes the registers used with the debugwire. 16.6.1 dwdr ? debugwire data register the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 0x20 (0x40) dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 163 8197c?avr?05/11 attiny261a/461a/861a 17. self-programming the flash the device provides a self-programming me chanism for downloading and uploading program code by the mcu itself. the self-programming ca n use any available data interface and associ- ated protocol to read code and write (program) that code into the program memory. the spm instruction is disabled by default but it ca n be enabled by programming the selfprgen fuse (to ?0?). the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. 17.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?00000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. note: the cpu is halted during the page erase operation. 17.2 filling the temporar y buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the ctpb bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. 164 8197c?avr?05/11 attiny261a/461a/861a if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 17.3 performing a page write to execute page write, set up the address in the z-pointer, write ?00000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. note: the cpu is halted during the page write operation. 17.4 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 18-7 on page 171 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 17-1 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the software addresses the same page in both the page erase and page write operation. the lpm instruction uses the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 17-1. addressing the flash during spm note: the different variables used in figure 17-1 are listed in table 18-7 on page 171 . bit 1514131211109 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 165 8197c?avr?05/11 attiny261a/461a/861a 17.5 eeprom write prevent s writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 17.6 reading fuse and lock bits from software it is possible for firmware to read device fuse and lock bits. note: fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unpro- grammed, will be read as one. 17.6.1 reading lock bits from firmware lock bit values are returned in the destination register after an lpm instruction has been issued within three cpu cycles after rflb and selfp rgen bits have been set in spmcsr. the rflb and selfprgen bits automatically clear upon completion of reading the lock bits, or if no lpm instruction is executed within three cpu cycl es, or if no spm instruction is executed within four cpu cycles. when rflb and selfpr gen are cleared lpm functions normally. to read the lock bits, follow the below procedure: 1. load the z-pointer with 0x0001. 2. set rflb and selfprgen bits in spmcsr. 3. issue an lpm instruction within three clock cycles. 4. read the lock bits from the lpm destination register. if successful, the contents of the destination register are as follows. see section ?program and data memory lock bits? on page 168 for more information. 17.6.2 reading fuse bits from firmware the algorithm for reading fuse byte s is similar to the one described above for reading lock bits, only the addresses are different. to read the fuse low byte (flb), follow the below procedure: 1. load the z-pointer with 0x0000. 2. set rflb and selfprgen bits in spmcsr. 3. issue an lpm instruction within three clock cycles. 4. read the flb from the lpm destination register. if successful, the contents of the destination register are as follows. refer to table 18-5 on page 170 for a detailed description and mapping of the fuse low byte. bit 76543210 rd ??????lb2lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 166 8197c?avr?05/11 attiny261a/461a/861a to read the fuse high byte (fhb), simply repl ace the address in the z-pointer with 0x0003 and repeat the procedure above. if successful, the contents of the destination register are as follows. refer to table 18-4 on page 169 for detailed description and mapping of the fuse high byte. to read the fuse extended byte (feb), replace the address in the z-pointer with 0x0002 and repeat the previous procedure. if successful, t he contents of the destination register are as follows. refer to table 18-3 on page 169 for detailed description and mapping of the fuse extended byte. 17.7 preventing fl ash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. keep the avr reset active (low) during peri ods of insufficient po wer supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 17.8 programming time fo r flash when using spm the calibrated oscillator is used to time flash accesses. table 17-1 shows the typical program- ming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd feb7 feb6 feb5 feb4 feb3 feb2 feb1 feb0 table 17-1. spm programming time (1) symbol min programming ti me max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 167 8197c?avr?05/11 attiny261a/461a/861a 17.9 register description 17.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to con- trol the program memory operations. ? bits 7:5 ? res: reserved bits these bits are reserved and always read as zero. ? bit 4 ? ctpb: clear temporary page buffer if the ctpb bit is writte n while filling the temporary page bu ffer, the temporary page buffer will be cleared and the da ta will be lost. ? bit 3 ? rflb: read fuse and lock bits an lpm instruction within three cycles after rflb and spmen are set in the spmcsr register, will read either the lock bits or t he fuse bits (depending on z0 in the z-pointer) in to the destina- tion register. see ?eeprom write preven ts writing to spmcsr? on page 165 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon co mpletion of a page write, or if no spm instruction is ex ecuted within four clock cycles. the cpu is halted during the entire page write operation. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bi t will auto-clear upon comp letion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either ctpb, rflb, pgwrt, or pgers, the following spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will aut o-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. bit 7 65 4 3 210 0x37 (0x57) ? ? ? ctpb rflb pgwrt pgers spmen spmcsr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 168 8197c?avr?05/11 attiny261a/461a/861a 18. memory programming this section describes the different methods for programming attiny261a/461a/861a memories. 18.1 program and data memory lock bits the device provides two lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional security listed in table 18-2 . the lock bits can only be erased to ?1? with the chip erase command. the device has no separate boot loader section. the spm instruction is enabled for the whole flash, if the selfprogen fuse is programmed (?0?), otherwise it is disabled. program memory can be read out via the debugwire interface when the dwen fuse is pro- grammed, even if lock bits are set. thus, when lock bit security is required, debugwire should always be disabled by clearing the dwen fuse. note: ?1? means unprogrammed, ?0? means programmed. notes: 1. program fuse bits before programming lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed. lock bits can also be read by device firmware. see section ?reading fuse and lock bits from software? on page 165 . table 18-1. lock bit byte lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) 5 ? 1 (unprogrammed) 4 ? 1 (unprogrammed) 3 ? 1 (unprogrammed) 2 ? 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 18-2. lock bit protection modes. memory lock bits (1) (2) protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in high-voltage and serial programming mode. the fuse bits are locked in both serial and high-voltage programming mode. (1) 300 further programming and verifica tion of the flash and eeprom is disabled in high-voltage and serial programming mode. the fuse bits are locked in both serial and high-voltage programming mode. (1) 169 8197c?avr?05/11 attiny261a/461a/861a 18.2 fuse bytes the device has three fuse bytes. table 18-3 , table 18-4 and table 18-5 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. notes: 1. enables spm instruction. see ?self-programming the flash? on page 163 . notes: 1. see ?alternate functions of port b? on page 65 for description of rstdisbl and dwen fuses. after programming the rstdisbl fuse, parallel programming must be used to change fuses and allow further programming. 2. dwen must be unprogrammed when lock bit security is required. see ?program and data memory lock bits? on page 168. 3. the spien fuse is not accessible in spi programming mode. 4. programming this fues will disable the watchdog timer interrupt. see ?wdtcr ? watchdog timer control register? on page 46 for details. 5. see table 19-6 on page 189 for bodlevel fuse decoding. table 18-3. fuse extended byte fuse high byte bit no de scription default value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) 5 - 1 (unprogrammed) 4 - 1 (unprogrammed) 3 - 1 (unprogrammed) 2 - 1 (unprogrammed) 1 - 1 (unprogrammed) selfprgen (1) 0 self-programming enable 1 (unprogrammed) table 18-4. fuse high byte fuse high byte bit no de scription default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen (2) 6 debugwire enable 1 (unprogrammed) spien (3) ) 6 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (4) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bodlevel2 (5) 2 brown-out detector trig ger level 1 (unprogrammed) bodlevel1 (5) 1 brown-out detector trig ger level 1 (unprogrammed) bodlevel0 (5) 0 brown-out detector trig ger level 1 (unprogrammed) 170 8197c?avr?05/11 attiny261a/461a/861a notes: 1. see ?system clock prescaler? on page 31 for details. 2. allows system clock to be output on pin. see ?clock output buffer? on page 32 for details. 3. the default value results in maximum start-up time for the default clock source. see table 6-7 on page 28 for details. 4. the default setting results in in ternal oscillator @ 8.0 mhz. see table 6-6 on page 28 for details. note that fuse bits are locked if lock bit 1 (lb1) is programmed. fuse bits should be pro- grammed before lock bits. the status of fuse bits is not affected by chip erase. fuse bits can also be read by device firmware. see section ?reading fuse and lock bits from software? on page 165 . 18.2.1 latching of fuses fuse values are latched when the device enters programming mode and changes to fuse values have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is prog rammed. fuses are also latched on power-up. 18.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and high-voltage programming mode, also when the device is locked. the three bytes reside in a separate address space. the signature bytes are given in table 18-6 . 18.4 calibration byte the signature area has one byte of calibration data for the in ternal oscillator. this byte resides in the high byte of address 0x000. during reset, this byte is automatically written into the osccal register to ensure correct frequ ency of the calibrated oscillator. table 18-5. fuse low byte fuse low byte bit no de scription default value ckdiv8 (1) 7 divide clock by 8 0 (programmed) ckout (2) 6 clock output enable 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (3) sut0 4 select start-up time 0 (programmed) (3) cksel3 3 select clock so urce 0 (programmed) (4) cksel2 2 select clock so urce 0 (programmed) (4) cksel1 1 select clock source 1 (unprogrammed) (4) cksel0 0 select clock so urce 0 (programmed) (4) table 18-6. device id parts signature bytes address 0x000 0x001 0x002 attiny261a 0x1e 0x91 0x0c attiny461a 0x1e 0x92 0x08 attiny861a 0x1e 0x93 0x0d 171 8197c?avr?05/11 attiny261a/461a/861a 18.5 page size 18.6 serial programming both the flash and eeprom memo ry arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). see figure 18-1 . figure 18-1. serial programming and verify note: if the device is clocked by the internal oscillat or, there is no need to connect a clock source to the clki pin. table 18-7. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb attiny261a 1k words (2k bytes) 16 words pc[3:0] 64 pc[9:4] 9 attiny461a 2k words (4k bytes) 32 words pc[4:0] 64 pc[10:5] 10 attiny861a 4k words (8k bytes) 32 words pc[4:0] 128 pc[11:5] 11 table 18-8. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb attiny261a 128 bytes 4 bytes eea[1:0] 32 eea[6:2] 6 attiny461a 256 bytes 4 bytes eea[1:0] 64 eea[7:2] 7 attiny861a 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 vcc gnd sck miso mosi reset +1.8 - 5.5v 172 8197c?avr?05/11 attiny261a/461a/861a after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note: in table 18-9 , above, the pin mapping for spi programming is listed. not all parts use the spi pins dedicated for the internal spi interface. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: ? low:> 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz ? high:> 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz 18.6.1 serial programming algorithm when writing serial data to the device, the data is clocked on the rising edge of sck. when reading, data is clocked on the falling edge of sck. see figure 19-3 and figure 19-4 for timing details. to program and verify the device in serial programming mode, the following sequence is recom- mended (see four byte instruction formats in table 18-11 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. ? in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse after sck has been set to '0'. the duration of the pulse must be at least t rst (the minimum pulse width on reset pin, see table 19-4 on page 188 ) plus two cpu clock cycles. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will no t work if the communic ation is out of syn- chronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 5 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 6 msb of the address. if polling (rdy/bsy) is not used, the user must wait at least t wd_flash table 18-9. pin mapping serial programming symbol pins i/o description mosi pb0 i serial data in miso pb1 o serial data out sck pb2 i serial clock 173 8197c?avr?05/11 attiny261a/461a/861a before issuing the next page. (see table 18-10 .) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. a: the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. if polling (rdy/bsy) is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 18-10 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. b: the eeprom array is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 2 lsb of the address and data together with the load eeprom memory page instruction. the eeprom me mory page is stored by loading the write eeprom memory page inst ruction with the 6 msb of the address. when using eeprom page access only by te locations loaded with the load eeprom memory page instruction is altered. the remaining locations remain unchanged. if poll- ing (rdy/bsy) is not used, the used must wait at least t wd_eeprom before issuing the next page (see table 18-8 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. 18.6.2 serial programming instruction set the instruction set is described in table 18-11 and figure 18-2 on page 175 . table 18-10. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 4.0 ms t wd_erase 9.0 ms t wd_fuse 4.5 ms table 18-11. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 174 8197c?avr?05/11 attiny261a/461a/861a notes: 1. not all instructions are applicable for all parts. 2. a = address 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?) . 5. refer to the correspondig section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word address. this address may be random within the page range. 7. see http://www.atmel.com/avr for application notes regarding programming and programmers. if the lsb in rdy/bsy data byte out is ?1?, a pr ogramming operation is still pending. wait until this bit returns ?0? before the ne xt instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buf fer, program the eeprom page, see figure 18-2 on page 175 . load program memory page, high byte $48 adr msb adr lsb high data byte in load program memory page, low byte $40 adr msb adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 $00 00aa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (6) write program memory page $4c adr msb adr lsb $00 write eeprom memory $c0 $00 00aa aaaa data byte in write eeprom memory page (page access) $c2 $00 00aa aa00 $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in table 18-11. serial programming instruction set (continued) instruction/operation instruction format byte 1 byte 2 byte 3 byte4 175 8197c?avr?05/11 attiny261a/461a/861a figure 18-2. serial programming instruction example 18.7 parallel programming this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits. pulses are assumed to be at least 250 ns in length, unless otherwise noted. 18.7.1 signal names in this section, some pins are referenced by signal names describing their functionality during parallel programming, see figure 18-3 and table 18-12 . pins not described in the following table are referenced by pin names. byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m ms sb a a adr r l lsb b 176 8197c?avr?05/11 attiny261a/461a/861a figure 18-3. parallel programming. table 18-12. pin name mapping signal name in programming mode pin name i/o function wr pb0 i write pulse (active low). xa0 pb1 i xtal action bit 0 xa1/bs2 pb2 i xtal action bit 1. byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte). pagel/bs1 pb3 i byte select 1 (?0? selects low byte, ?1? selects high byte). program memory and eeprom data page load. oe pb5 i output enable (active low). rdy/bsy pb6 o 0: device is busy programming, 1: device is ready for new command. data i/o pa7-pa0 i/o bi-directional data bus (output when oe is low). vcc +5v gnd xt al1/pb4 pb6 pb5 pb0 pb3 pb1 pb2 pa7 - pa0 data reset +12 v pagel/bs1 xa0 xa1/bs2 oe rdy/bsy wr avcc +5v 177 8197c?avr?05/11 attiny261a/461a/861a the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 18-14 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 18-15 . table 18-13. pin values used to enter programming mode pin symbol value pagel/bs1 prog_enable[3] 0 xa1/bs2 prog_enable[2] 0 xa0 prog_enable[1] 0 wr prog_enable[0] 0 table 18-14. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom addr ess (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 18-15. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 178 8197c?avr?05/11 attiny261a/461a/861a 18.7.2 entering programming mode the following algorithm puts the devi ce in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set prog_enable pins listed in table 18-13 on page 177 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50 s before sending a new command. 18.7.3 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered: ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 18.7.4 chip erase the chip erase will erase the flash and eeprom memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. 1. load command ?chip erase?: a. set xa1, xa0 to ?10?. this enables command loading. b. set bs1 to ?0?. c. set data to ?1000 0000?. this is the command for chip erase. d. give xtal1 a positive pulse. this loads the command. e. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. f. wait until rdy/bsy goes high before loading a new command. note: the eeprom memory is preserved during chip erase if the eesave fuse is programmed. 18.7.5 programming the flash the flash is organized in pages, see table 18-7 on page 171 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory (see figure 18-5 for signal waveforms): 179 8197c?avr?05/11 attiny261a/461a/861a 1. load command ?write flash?: a. set xa1, xa0 to ?10?. this enables command loading. b. set bs1 to ?0?. c. set data to ?0001 0000?. this is the command for write flash. d. give xtal1 a positive pulse. this loads the command. 2. load address low byte: a. set xa1, xa0 to ?00?. this enables address loading. b. keep bs1 at ?0?. this selects low address. c. set data = address low byte (0x00 - 0xff). d. give xtal1 a positive pulse. this loads the address low byte. 3. load data low byte: a. set xa1, xa0 to ?01?. this enables data loading. b. set data = data low byte (0x00 - 0xff). c. give xtal1 a positive pulse. this loads the data byte. 4. load data high byte: a. set bs1 to ?1?. this selects high data byte. b. keep xa1, xa0 at ?01?. this enables data loading. c. set data = data high byte (0x00 - 0xff). d. give xtal1 a positive pulse. this loads the data byte. 5. repeat steps 2 to 4 until the entire buffer is filled or until all data within the page is loaded. 6. load address high byte: a. set xa1, xa0 to ?00?. this enables address loading. b. set bs1 to ?1?. this selects high address. c. set data = address high byte (0x00 - 0xff). d. give xtal1 a positive pulse. this loads the address high byte. 7. program page: a. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. b. wait until rdy/bsy goes high. 8. repeat steps 2 to 7 until the entire flash is programmed or until all data has been programmed. 9. end page programming: a. set xa1, xa0 to ?10?. this enables command loading. b. set data to ?0000 0000?. this is the command for no operation. c. give xtal1 a positive pulse. this loads the command, and the internal write sig- nals are reset. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 18-4 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. 180 8197c?avr?05/11 attiny261a/461a/861a figure 18-4. addressing the flash which is organized in pages note: pcpage and pcword are listed in table 18-7 on page 171 . in the figure below, ?xx? means don?t care. the numbers in the figure refer to the programming description above. wr figure 18-5. flash programming waveforms 18.7.6 programming the eeprom the eeprom is organized in pages, see table 18-8 on page 171 . when programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 0x10 addr. low data low addr. high data high data low addr. low data high data xa1 / bs2 xa0 pagel / bs1 xtal1 wr rdy / bsy reset +12v oe xxx 1 step 7 5 6 4 3 2 4 3 2 8 0x00 9 181 8197c?avr?05/11 attiny261a/461a/861a programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 178 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). 6. k: repeat 3 through 5 until the entire buffer is filled. 7. l: program eeprom page a. set bs to ?0?. b. give wr a negative pulse. this starts programming of the eeprom page. rdy/bsy goes low. c. wait until to rdy/bsy goes high before programming the next page (see figure 18-6 for signal waveforms). figure 18-6. programming the eeprom waveforms 18.7.7 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 178 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. rdy/bsy wr oe reset +12v 0x11 addr. high data addr. low data addr. low data xx xa1/bs2 xa0 pagel/bs1 xtal1 xx agbceb c el k 182 8197c?avr?05/11 attiny261a/461a/861a 18.7.8 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 178 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 18.7.9 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 178 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 18.7.10 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 178 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 18.7.11 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 178 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. 183 8197c?avr?05/11 attiny261a/461a/861a figure 18-7. programming t he fuses waveforms 18.7.12 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 178 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 18.7.13 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 178 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. rdy/bsy wr oe reset +12v 0x40 data data xx xa1/bs2 xa0 pagel/bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte 184 8197c?avr?05/11 attiny261a/461a/861a figure 18-8. mapping between bs1, bs2 and the fuse and lock bits during read 18.7.14 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 178 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 18.7.15 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 178 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 185 8197c?avr?05/11 attiny261a/461a/861a 19. electrical characteristics 19.1 absolute maximum ratings* 19.2 dc characteristics operating temperature.................................. -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin except reset with respect to ground ............................... -0.5v to v cc +0.5v voltage on reset with respect to ground......-0.5v to +13.0v maximum operating voltage ............................................ 6.0v dc current per i/o pin ............................................... 40.0 ma dc current v cc and gnd pins ................................ 200.0 ma table 19-1. dc characteristics. t a = -40 c to +85 c, v cc = 1.8v to 5.5v (unless otherwise noted). symbol parameter condition min typ (1) max units v il input low-voltage except xtal1 and reset pins -0.5 0.2v cc (3) v xtal1 pin, external clock selected -0.5 0.1v cc (3) v reset pin -0.5 0.2v cc (3) v reset pin as i/o -0.5 0.2v cc (3) v v ih input high-voltage except xtal1 and reset pins 0.7v cc (2) v cc +0.5 v xtal1 pin, external clock selected 0.8v cc (2) v cc +0.5 v reset pin 0.9v cc (2) v cc +0.5 v reset pin as i/o 0.7v cc (2) v cc +0.5 v v ol output low voltage (4) , except high sink i/o pins and reset pin as i/o (6) i ol = 10 ma, v cc = 5v 0.6 v i ol = 5 ma, v cc = 3v 0.5 v i ol = 2 ma, v cc = 1.8v 0.4 v output low voltage reset pin as i/o (6) i ol = 2 ma, v cc = 5v 0.6 v i ol = 1 ma, v cc = 3v 0.5 v i ol = 0.4 ma, v cc = 1.8v 0.4 v v oh output high voltage (5) , except high sink i/o pins and reset pin as i/o (6) i oh = -10 ma, v cc = 5v 4.3 v i oh = -5 ma, v cc = 3v 2.5 v i oh = -2 ma, v cc = 1.8v 1.4 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) < 0.05 1 a 186 8197c?avr?05/11 attiny261a/461a/861a notes: 1. typical values at +25 c. 2. ?min? means the lowest value where t he pin is guaranteed to be read as high. 3. ?max? means the highest value where the pin is guaranteed to be read as low. 4. although each i/o port can sink more than the test conditions (10 ma at v cc = 5v, 5 ma at v cc = 3v) under steady state conditions (non-transient), the sum of all i ol (for all ports) should not exceed 100 ma. if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guarante ed to sink current greater th an the listed test condition. 5. although each i/o port can source more than the test conditions (10 ma at v cc = 5v, 5 ma at v cc = 3v) under steady state conditions (non-transient), the sum of all i oh (for all ports) should not exceed 100 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 6. the reset pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared to regular i/o pins. see figure 20-32 , figure 20-33 , figure 20-34 , and figure 20-35 (starting on page 214 ). 7. values are with external clock using methods described in ?minimizing power consumption? on page 37 . power reduction is enabled (prr = 0xff) and there is no i/o drive. 8. bod disabled. i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) < 0.05 1 a r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 k i cc power supply current (7) active 1mhz, v cc = 2v 0.2 0.5 ma active 4mhz, v cc = 3v 1.2 2 ma active 8mhz, v cc = 5v 3.6 7 ma idle 1mhz, v cc = 2v 0.04 0.15 ma idle 4mhz, v cc = 3v 0.25 0.4 ma idle 8mhz, v cc = 5v 0.9 1.5 ma power-down mode (8) wdt enabled, v cc = 3v 4 10 a wdt disabled, v cc = 3v 0.15 2 a table 19-1. dc characteristics. t a = -40 c to +85 c, v cc = 1.8v to 5.5v (unless otherwise noted). symbol parameter condition min typ (1) max units 187 8197c?avr?05/11 attiny261a/461a/861a 19.3 speed the maximum operating frequency of the device is dependent on supply voltage, v cc . the rela- tionship between supply voltage and maximum operating frequency is piecewise linear, as shown in figure 19-1 . figure 19-1. maximum operating frequency vs. supply voltage 19.4 clock characteristics 19.4.1 accuracy of calibrated internal oscillator it is possible to manua lly calibrate the internal oscillator to be more accu rate than def ault factory calibration. note that the osc illator frequency depend s on temperat ure and voltage. voltage and temperature characteristics can be found in figure 20-49 on page 223 and figure 20-50 on page 223 . notes: 1. accuracy of oscillator frequency at calibra tion point (fixed temperature and fixed voltage). 4 mhz 1. 8 v 5.5v 4.5v 20 mhz 2.7v 10 mhz table 19-2. calibration accuracy of internal oscillator calibration method target frequency v cc temperature accuracy at given voltage & temperature (1) factory calibration 8.0 mhz 3v 25 c 10% user calibration fixed frequency within: 7.3 - 8.1 mhz fixed voltage within: 1.8v - 5.5v fixed temperature within: -40 c to +85 c 1% 188 8197c?avr?05/11 attiny261a/461a/861a 19.4.2 external clock drive figure 19-2. external clock drive waveforms 19.5 system and reset characteristics notes: 1. not tested. values are guidelines, only. v il1 v ih1 table 19-3. external clock drive characteristics symbol parameter v cc = 1.8 - 5.5v v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. min. max. 1/t clcl clock frequency 0 4 0 10 0 20 mhz t clcl clock period 250 100 50 ns t chcx high time 100 40 20 ns t clcx low time 100 40 20 ns t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 s t clcl change in period from one clock cycle to the next 2 2 2 % table 19-4. reset, brown-out, and internal voltage characteristics symbol parameter condition min typ max units v rst reset pin threshold voltage (1) 0.2 v cc 0.9 v cc v t rst min pulse width on reset pin (1) v cc = 3v 2.5 s v hyst brown-out detector hysteresis (1) 50 mv t bod min pulse width on brown-out reset (1) 2s v bg internal bandgap voltage v cc = 2.7v t a =25c 1.0 1.1 1.2 v t bg internal bandgap start-up time (1) v cc = 5v t a =25c 40 70 s i bg internal bandgap reference current consumption (1) v cc = 5v t a =25c 15 a 189 8197c?avr?05/11 attiny261a/461a/861a 19.5.1 enhanced power-on reset note: 1. values are guidelines, only. 2. threshold where device is released from reset when voltage is rising. 3. the power-on reset will not work unless the supply voltage has been below v poa . 19.5.2 brown-out detection note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. table 19-5. characteristics of enhanced power-on reset. t a = -40 to +85 c symbol parameter min (1) typ (1) max (1) units v por release threshold of power-on reset (2) 1.1 1.4 1.6 v v poa activation threshold of power-on reset (3) 0.6 1.3 1.6 v sr on power-on slope rate 0.01 v/ms table 19-6. bodlevel fuse coding (1) bodlevel[2:0] fuses min v bot typ v bot max v bot units 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.1 4.3 4.5 0xx reserved 190 8197c?avr?05/11 attiny261a/461a/861a 19.6 adc characteristics table 19-7. adc characteristics, single ended channels. t = -40 c to +85 c symbol parameter condition min typ max units resolution 10 bits absolute accuracy (including inl, dnl, and quantization, gain and offset errors) v ref = 4v, v cc = 4v, adc clock = 200 khz 2lsb v ref = 4v, v cc = 4v, adc clock = 1 mhz 3lsb v ref = 4v, v cc = 4v, adc clock = 200 khz noise reduction mode 1.5 lsb v ref = 4v, v cc = 4v, adc clock = 1 mhz noise reduction mode 2.5 lsb integral non-linearity (inl) (accuracy after offset and gain calibration) v ref = 4v, v cc = 4v, adc clock = 200 khz 1lsb differential non-linearity (dnl) v ref = 4v, v cc = 4v, adc clock = 200 khz 0.5 lsb gain error v ref = 4v, v cc = 4v, adc clock = 200 khz 2.5 lsb offset error v ref = 4v, v cc = 4v, adc clock = 200 khz 1.5 lsb conversion time free running conversion 13 260 s clock frequency 50 1000 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v a ref external voltage reference 2.0 avcc v v in input voltage gnd v ref input bandwidth 38.5 khz v int internal 1.1v reference 1.0 1.1 1.2 v internal 2.56v reference v cc > 3.0v 2.3 2.56 2.8 v r ref reference input resistance 35 k r ain analog input resistance 100 m adc conversion output 0 1023 lsb 191 8197c?avr?05/11 attiny261a/461a/861a notes: 1. v diff must be below v ref . table 19-8. adc characteristics, dif ferential channels (unipolar mode). t = -40 c to +85 c symbol parameter condition min typ max units resolution gain = 1x / 8x / 20x / 32x 10 bits absolute accuracy (including inl, dnl, and quantization, gain and offset errors) gain = 1x / 8x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 10 lsb gain = 20x / 32x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 15 lsb integral non-linearity (inl) (accuracy after offset and gain calibration) gain = 1x / 8x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 4lsb gain = 20x / 32x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 10 lsb gain error gain = 1x / 8x 10 lsb gain = 20x / 32x 15 lsb offset error gain = 1x / 8x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 3lsb gain = 20x / 32x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 4lsb conversion time free running conversion 65 260 s clock frequency 50 200 khz v in input voltage gnd av cc (1) v v diff input differential voltage v ref /gain v input bandwidth 4 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v a ref external voltage reference 2.0 avcc - 1.0 v v int internal 1.1v reference 1.0 1.1 1.2 v internal 2.56v reference v cc > 3.0v 2.3 2.56 2.8 v r ref reference input resistance 35 k r ain analog input resistance 100 m adc conversion output 0 1023 lsb 192 8197c?avr?05/11 attiny261a/461a/861a notes: 1. v diff must be below v ref . table 19-9. adc characteristics, dif ferential channels (bipolar mode). t = -40 c to +85 c symbol parameter condition min typ max units resolution gain = 1x / 8x / 20x / 32x 10 bits absolute accuracy (including inl, dnl, and quantization, gain and offset errors) gain = 1x / 8x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 8lsb gain = 20x / 32x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 8lsb integral non-linearity (inl) (accuracy after offset and gain calibration) gain = 1x / 8x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 4lsb gain = 20x / 32x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 5lsb gain error gain = 1x / 8x 4 lsb gain = 20x / 32x 5 lsb offset error gain = 1x / 8x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 3lsb gain = 20x / 32x v ref = 4v, v cc = 5v adc clock = 50 - 200 khz 4lsb conversion time free running conversion 65 260 s clock frequency 50 200 khz v in input voltage gnd av cc (1) v v diff input differential voltage v ref /gain v input bandwidth 4 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v a ref external voltage reference 2.0 avcc - 1.0 v v int internal 1.1v reference 1.0 1.1 1.2 v internal 2.56v reference v cc > 3.0v 2.3 2.56 2.8 v r ref reference input resistance 35 k r ain analog input resistance 100 m adc conversion output -512 511 lsb 193 8197c?avr?05/11 attiny261a/461a/861a 19.7 analog comparat or characteristics 19.8 serial programming characteristics figure 19-3. serial programming waveforms figure 19-4. serial programming timing table 19-10. analog comparator characteristics, t a = -40 c to +85 c symbol parameter condi tion min typ max units v aio input offset voltage v cc = 5v, vin = v cc / 2 < 10 40 mv i lac input leakage current v cc = 5v, vin = v cc / 2 -50 50 na t apd analog propagation delay (from saturation to slight overdrive) v cc = 2.7v 750 ns v cc = 4.0v 500 analog propagation delay (large step change) v cc = 2.7v 100 v cc = 4.0v 75 t dpd digital propagation delay v cc = 1.8v - 5.5 1 2 clk msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output mosi miso sck t ovsh t shsl t slsh t shox t sliv 194 8197c?avr?05/11 attiny261a/461a/861a note: 1. 2 t clcl for f ck < 12 mhz, 3 t clcl for f ck >= 12 mhz 19.9 parallel programmi ng characteristics figure 19-5. parallel programming timing, including some general timing requirements table 19-11. serial programming characteristics, t a = -40 c to +85 c, v cc = 1.8 - 5.5v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency 0 4 mhz t clcl oscillator period 250 ns 1/t clcl oscillator frequency (v cc = 4.5v - 5.5v) 0 20 mhz t clcl oscillator period v cc = 4.5v - 5.5v 50 ns t shsl sck pulse width high 2 t clcl (1) ns t slsh sck pulse width low 2 t clcl (1) ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 100 ns data & contol (data, xa0, xa1/bs2, pagel/bs1) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy t plbx t bvph t xlwl t wlbx t bvwl wlrl 195 8197c?avr?05/11 attiny261a/461a/861a figure 19-6. parallel programming timing, loading sequence with timing requirements note: the timing requirements shown in figure 19-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 19-7. parallel programming timing, read ing sequence (within the same page) with timing requirements note: the timing requirements shown in figure 19-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 xlxh t addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low byte) load data (low byte) load data (high byte) load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data pagel/bs1 xa0 xa1/bs2 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz table 19-12. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns 196 8197c?avr?05/11 attiny261a/461a/861a notes: 1. t wlrh is valid for the write flash, write eepro m, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns table 19-12. parallel programming characteristics, v cc = 5v 10% (continued) symbol parameter min typ max units 197 8197c?avr?05/11 attiny261a/461a/861a 20. typical characteristics the data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. thus, the data should be treated as indica- tions of how the part will behave. the following charts show typical behavior. t hese figures are not tested during manufacturing. during characterisation devices are operated at fr equencies higher than test limits but they are not guaranteed to function properly at frequencies higher than the ordering code indicates. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups enabled. current consumption is a function of several factors such as oper- ating voltage, operating frequency, loading of i/o pins, switching rate of i/o pins, code executed and ambient temperature. the dominating factors are operating voltage and frequency. a sine wave generator with rail-to-rail output is used as clock source but current consumption in power-down mode is independent of clock selection. the difference between current consump- tion in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. the current drawn from pins with a capacitive lo ad may be estimated (for one pin) as follows: where v cc = operating voltage, c l = load capacitance and f sw = average switching frequency of i/o pin. 20.1 supply current of i/o modules the tables and formulas below can be used to calculate the additional current consumption for the different i/o modules in active and idle mode. the enabling or disabling of the i/o modules are controlled by the power reduction register. see ?prr ? power reduction register? on page 39 for details. table 20-2 below can be used for calculating typical current consumption for other supply volt- ages and frequencies than those mentioned in table 20-1 above. i cp v cc c l f sw table 20-1. additional current consumption for the different i/o modules (absolute values). prr bit typical numbers v cc = 2v, f = 1mhz v cc = 3v, f = 4mhz v cc = 5v, f = 8mhz prtim1 35 a 200 a 900 a prtim0 5 a 25 a 100 a prusi 5 a 25 a 450 a pradc 200 a 280 a 550 a 198 8197c?avr?05/11 attiny261a/461a/861a it is possible to calculate the typical current consumption based on the numbers from table 20-1 for other v cc and frequency settings than listed in table 20-2 . 20.1.1 example calculate the expected current consumption in idle mode with timer0, adc, and usi enabled at v cc = 2.0v and f = 1 mhz. from table 20-2 , third column, we see that we need to add 10% for the timer0, 27.3 % for the adc, and 6.5 % for the usi module. reading from figure 20-6 on page 201 , we find that the idle current consumption is ~0,085 ma at v cc = 2.0v and f = 1 mhz. the total current consumption in idle mode with timer0, adc, and usi enabled, gives: table 20-2. additional current consumption (percentage) in active and idle mode. prr bit additional current consumption compared to active with external clock (see figure 20-1 on page 199 and figure 20-2 on page 199 ) additional current consumption compared to idle with external clock (see figure 20-6 on page 201 and figure 20-7 on page 202 ) prtim1 20...25 % 100 % prtim0 2...3 % 10...15 % prusi 2...12 % 10...50% pradc 15...100 % 50...500 % i cc total 0.085 ma 10.100.2730.065 ++ + () ? 0.122 ma ? 199 8197c?avr?05/11 attiny261a/461a/861a 20.2 attiny261a 20.2.1 current consumption in active mode figure 20-1. active supply current vs. low frequency (0.1 - 1.0 mhz) figure 20-2. active supply current vs. frequency (1 - 20 mhz) active s upply current v s . low frequency 5.5 v 5.0 v 4.5 v 3 . 3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) active s upply current v s . frequency prr = 0xff 5.5 v 5.0 v 4.5 v 3 . 3 v 2.7 v 1. 8 v 0 2 4 6 8 10 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 200 8197c?avr?05/11 attiny261a/461a/861a figure 20-3. active supply current vs. v cc (internal ca librated oscillator, 8 mhz) figure 20-4. active supply current vs. v cc (internal ca librated oscillator, 1 mhz) active s upply current v s . s upply voltage internal o s cillator, 8 mhz 8 5 c 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) active s upply current v s . s upply voltage internal o s cillator, 1 mhz 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 201 8197c?avr?05/11 attiny261a/461a/861a figure 20-5. active supply current vs. v cc (internal ca librated oscillator, 128 khz) 20.2.2 current consumption in idle mode figure 20-6. idle supply current vs. low frequency (0.1 - 1.0 mhz) active s upply current v s . s upply voltage internal o s cillator, 12 8 khz 8 5 c 25 c -40 c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) idle s upply current v s . low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 202 8197c?avr?05/11 attiny261a/461a/861a figure 20-7. idle supply current vs. frequency (1 - 20 mhz) figure 20-8. idle supply current vs. v cc (internal ca librated oscillator, 8 mhz) idle s upply current v s . frequency 5.5 v 5.0 v 4.5 v 4.0 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) idle s upply current v s . v cc internal o s cillator, 8 mhz 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) icc (ma) 203 8197c?avr?05/11 attiny261a/461a/861a figure 20-9. idle supply current vs. v cc (internal ca librated oscillator, 1 mhz) figure 20-10. idle supply current vs. v cc (internal ca librated oscillator, 128 khz) idle s upply current v s . v cc internal o s cillator, 1 mhz 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) idle s upply current v s . v cc internal o s cillator, 12 8 khz 8 5 c 25 c -40 c 0 0.005 0.01 0.015 0.02 0.025 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 204 8197c?avr?05/11 attiny261a/461a/861a 20.2.3 current consumption in power-down mode figure 20-11. power-down supply current vs. v cc (watchdog timer disabled) figure 20-12. power-down supply current vs. v cc (watchdog timer enabled) power-down s upply current v s . s upply voltage watchdog timer di s abled 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) power-down s upply current v s . s upply voltage watchdog timer enabled 8 5 c 25 c -40 c 0 2 4 6 8 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 205 8197c?avr?05/11 attiny261a/461a/861a 20.2.4 current consumption in reset figure 20-13. reset supply current vs. low frequency (0.1 - 1.0 mhz, excluding current through the reset pull-up) figure 20-14. reset supply current vs. frequency (1 - 20 mhz, excluding current through the reset pull-up) re s et current v s . frequency excluding current through re s et pullup 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) re s et current v s . s upply voltage excluding current through re s et pullup 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) icc (ma) 206 8197c?avr?05/11 attiny261a/461a/861a 20.2.5 current consumption of peripheral units figure 20-15. analog comparator current vs. v cc figure 20-16. adc current vs. v cc (aref = av cc ) analog comparator current v s . v cc 0 10 20 3 0 40 50 60 70 8 0 1.5 2 2.5 33 .544.555.5 v cc (v) i cc ( u a) adc current v s . v cc f = 1.0 mhz 0 50 100 150 200 250 3 00 3 50 400 450 1.5 2 2.5 33 .544.555.5 v cc (v) i cc ( u a) 207 8197c?avr?05/11 attiny261a/461a/861a figure 20-17. timer/counter1 current vs. v cc figure 20-18. brownout detector current vs. v cc timer/counter1 current v s . v cc 64mhz 3 2mhz 1mhz 0 1000 2000 3 000 4000 5000 6000 7000 8 000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) brownout detector current v s . v cc 0 5 10 15 20 25 3 0 3 5 40 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 208 8197c?avr?05/11 attiny261a/461a/861a figure 20-19. programming current vs. v cc 20.2.6 pull-up resistors figure 20-20. pull-up resistor current vs. input voltage (i/o pin, v cc = 1.8v) programming current v s . v cc 0 1000 2000 3 000 4000 5000 6000 7000 8 000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) i/o pin pull-up resistor current vs. input voltage v cc = 1.8v 85 ?c 25 ?c -40 ?c 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v op (v) i op (ua) 209 8197c?avr?05/11 attiny261a/461a/861a figure 20-21. pull-up resistor current vs. input voltage (i/o pin, v cc = 3v) figure 20-22. pull-up resistor current vs. input voltage (i/o pin, v cc = 5v) i/o pin pull-up resistor current vs. input voltage v cc = 2.7v 85 ?c 25 ?c -40 ?c 0 10 20 30 40 50 60 70 80 90 0 0,5 1 1,5 2 2,5 3 v op (v) i op (ua) i/o pin pull-up resistor current vs. input voltage v cc = 5v 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 210 8197c?avr?05/11 attiny261a/461a/861a figure 20-23. pull-up resistor current vs. input voltage (reset pin, v cc = 1.8v) figure 20-24. pull-up resistor current vs. input voltage (reset pin, v cc = 3v) re s et pull-up re s i s tor current v s . re s et pin voltage 8 5 c 25 c -40 c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v re s et (v) i re s et ( u a) v cc = 1. 8 v v cc = 3 v re s et pull-up re s i s tor current v s . re s et pin voltage 0 10 20 3 0 40 50 60 0 0.5 1 1.5 2 2.5 3 v re s et (v) i re s et ( u a) 8 5 c 25 c -40 c 211 8197c?avr?05/11 attiny261a/461a/861a figure 20-25. pull-up resistor current vs. input voltage (reset pin, v cc = 5v) 20.2.7 output driver strength figure 20-26. v ol : output voltage vs. sink current (i/o pin, v cc = 1.8v) v cc = 5v 8 5 c 25 c -40 c re s et pull-up re s i s tor current v s . re s et pin voltage 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 33 .5 4 4.5 5 v re s et (v) i re s et ( u a) i/o pin output voltage v s . s ink current v cc = 1. 8 v 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 012 3 45 i ol (ma) v ol (v) 212 8197c?avr?05/11 attiny261a/461a/861a figure 20-27. v ol : output voltage vs. sink current (i/o pin, v cc = 3v) figure 20-28. v ol : output voltage vs. sink current (i/o pin, v cc = 5v) i/o pin output voltage v s . s ink current v cc = 3 v 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0246 8 10 i ol (ma) v ol (v) i/o pin output voltage v s . s ink current v cc = 5v 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0246 8 10 12 14 16 1 8 20 i ol (ma) v ol (v) 213 8197c?avr?05/11 attiny261a/461a/861a figure 20-29. v oh : output voltage vs. source current (i/o pin, v cc = 1.8v) figure 20-30. v oh : output voltage vs. source current (i/o pin, v cc = 3v) i/o pin output voltage v s . s ource current v cc = 1. 8 v 8 5 c 25 c -40 c 1. 3 1.4 1.5 1.6 1.7 1. 8 012 3 45 i oh (ma) v oh (v) i/o pin output voltage v s . s ource current v cc = 3 v 8 5 c 25 c -40 c 2.5 2.6 2.7 2. 8 2.9 3 0246 8 10 i oh (ma) v oh (v) 214 8197c?avr?05/11 attiny261a/461a/861a figure 20-31. v oh : output voltage vs. source current (i/o pin, v cc = 5v) figure 20-32. v ol : output voltage vs. sink current (reset pin as i/o, v cc = 5v) i/o pin output voltage v s . s ource current v cc = 5v 8 5 c 25 c -40 c 4.2 4.4 4.6 4. 8 5 0 5 10 15 20 i oh (ma) v oh (v) output voltage v s . s ink current re s et pin a s i/o 25 c -40 c 0 0.2 0.4 0.6 0. 8 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 i ol (ma) v ol (v) 8 5 c 215 8197c?avr?05/11 attiny261a/461a/861a figure 20-33. v ol : output voltage vs. sink current (reset pin as i/o, t = 25c) figure 20-34. v oh : output voltage vs. source current (reset pin as i/o, v cc = 5v) output voltage v s . s ink current re s et pin a s i/o 3 .0 v 5.0 v 0 0.2 0.4 0.6 0. 8 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 i ol (ma) v ol (v) 1. 8 v output voltage v s . s ource current re s et pin a s i/o, v cc = 5v 8 5 c 25 c -40 c 0 1 2 3 4 5 0 0.2 0.4 0.6 0. 8 1 i oh (ma) v oh (v) 216 8197c?avr?05/11 attiny261a/461a/861a figure 20-35. v oh : output voltage vs. source current (reset pin as i/o, t = 25c) 20.2.8 input thresholds and hysteresis figure 20-36. v ih : input threshold voltage vs. v cc (i/o pin, read as ?1?) output voltage v s . s ource current re s et pin a s i/o 1. 8 v 3 .0 v 5.0 v 0 1 2 3 4 5 0 0.2 0.4 0.6 0. 8 1 i oh (ma) v oh (v) i/o pin input thre s hold v s . s upply voltage v ih , i/o pin read a s '1' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 217 8197c?avr?05/11 attiny261a/461a/861a figure 20-37. v il : input threshold voltage vs. v cc (i/o pin, read as ?0?) figure 20-38. v ih -v il : input hysteresis vs. v cc (i/o pin) i/o pin input thre s hold v s . s upply voltage v il , i/o pin read a s '0' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) i/o pin input hy s tere s i s v s . s upply voltage 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 218 8197c?avr?05/11 attiny261a/461a/861a figure 20-39. v ih : input threshold voltage vs. v cc (reset pin, read as ?1?) figure 20-40. v il : input threshold voltage vs. v cc (reset pin, read as ?0?) re s et input thre s hold voltage v s . vcc v ih , pin read a s '1' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .544.555.5 v cc (v) thre s hold (v) re s et input thre s hold voltage v s . vcc v il , pin read a s '0' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .544.555.5 v cc (v) thre s hold (v) 219 8197c?avr?05/11 attiny261a/461a/861a figure 20-41. v ih -v il : input hysteresis vs. v cc (reset pin) 20.2.9 bod, bandgap and reset figure 20-42. bod threshold vs. temperature (bod level set to 4.3v) re s et pin input hy s tere s i s v s . v cc 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 1.5 2 2.5 33 .544.555.5 v cc (v) inp u t hy s tere s i s (v) v cc ri s ing v cc falling bod thre s hold s v s . temperature bodlevel = 4. 3 v 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 4. 3 6 4. 38 -40 -20 0 20 40 60 8 0 100 temper a t u re (c) thre s hold (v) 220 8197c?avr?05/11 attiny261a/461a/861a figure 20-43. bod threshold vs. temperature (bod level set to 2.7v) figure 20-44. bod threshold vs. temperature (bod level set to 1.8v) v cc ri s ing v cc falling bod thre s hold s v s . temperature bodlevel = 2.7v 2.66 2.6 8 2.7 2.72 2.74 2.76 2.7 8 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) bod thre s hold s v s . temperature bodlevel = 1. 8 v v cc ri s ing 1.7 8 1.79 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 1. 8 5 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) v cc falling 221 8197c?avr?05/11 attiny261a/461a/861a figure 20-45. bandgap voltage vs. supply voltage. figure 20-46. minimum reset pulse width vs. v cc bandgap voltage v s . v cc 8 5 c 25 c -40 c 1.07 1.0 8 1.09 1.1 1.11 1.5 2.5 3 .5 4.5 5.5 v cc (v) b a ndg a p volt a ge (v) minimum re s et pul s e width v s . v cc 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 222 8197c?avr?05/11 attiny261a/461a/861a 20.2.10 internal oscillators figure 20-47. frequency of watchd og oscillator vs. v cc figure 20-48. frequency of watc hdog oscillator vs. temperature watchdog o s cillator frequency v s . s upply voltage 8 5 c 25 c -40 c 110000 115000 120000 125000 1 3 0000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) fre qu ency (hz) watchdog o s cillator frequency v s . temperature 5.0 v 3 .0 v 1. 8 v 110000 115000 120000 125000 1 3 0000 -40 -20 0 20 40 60 8 0 100 temper a t u re fre qu ency (khz) 223 8197c?avr?05/11 attiny261a/461a/861a figure 20-49. frequency of calibrated 8.0 mhz oscillator vs. v cc figure 20-50. frequency of calibra ted 8.0 mhz oscillato r vs. temperature calibrated 8 mhz o s cillator frequency v s . s upply voltage 7.6 7. 8 8 8 .2 8 .4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) fre qu ency (mhz) 8 5 c 25 c -40 c calibrated 8 mhz o s cillator frequency v s . temperature 5.0 v 3 .0 v 1. 8 v 7. 8 7.9 8 8 .1 8 .2 -40 -20 0 20 40 60 8 0 100 temper a t u re fre qu ency (mhz) 224 8197c?avr?05/11 attiny261a/461a/861a figure 20-51. frequency of calibra ted 8.0 mhz oscillator vs. osccal value calibrated 8 mhz o s cillator frequency v s . o s ccal value 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 16 016 3 24 8 64 8 09611212 8 144 160 176 192 20 8 224 240 o s ccal (x1) frc (mhz) 225 8197c?avr?05/11 attiny261a/461a/861a 20.3 attiny461a 20.3.1 current consumption in active mode figure 20-52. active supply current vs. low frequency (0.1 - 1.0 mhz) figure 20-53. active supply current vs. frequency (1 - 20 mhz) active s upply current v s . low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) active s upply current v s . frequency prr = 0xff 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 2 4 6 8 10 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 226 8197c?avr?05/11 attiny261a/461a/861a figure 20-54. active supply current vs. v cc (internal ca librated oscillator, 8 mhz) figure 20-55. active supply current vs. v cc (internal ca librated oscillator, 1 mhz) 8 5 c 25 c -40 c active s upply current v s . s upply voltage internal o s cillator, 8 mhz 0 1 2 3 4 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) active s upply current v s . s upply voltage internal o s cillator, 1 mhz 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 227 8197c?avr?05/11 attiny261a/461a/861a figure 20-56. active supply current vs. v cc (internal ca librated oscillator, 128 khz) 20.3.2 current consumption in idle mode figure 20-57. idle supply current vs. low frequency (0.1 - 1.0 mhz) active s upply current v s . s upply voltage internal o s cillator, 12 8 khz 8 5 c 25 c -40 c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) idle s upply current v s . low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 228 8197c?avr?05/11 attiny261a/461a/861a figure 20-58. idle supply current vs. frequency (1 - 20 mhz) figure 20-59. idle supply current vs. v cc (internal ca librated oscillator, 8 mhz) idle s upply current v s . frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) idle s upply current v s . v cc internal o s cillator, 8 mhz 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .544.555.5 v cc (v) icc (ma) 229 8197c?avr?05/11 attiny261a/461a/861a figure 20-60. idle supply current vs. v cc (internal ca librated oscillator, 1 mhz) figure 20-61. idle supply current vs. v cc (internal ca librated oscillator, 128 khz) idle s upply current v s . v cc internal o s cillator, 1 mhz 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) idle s upply current v s . v cc internal o s cillator, 12 8 khz 8 5 c 25 c -40 c 0 0.005 0.01 0.015 0.02 0.025 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 230 8197c?avr?05/11 attiny261a/461a/861a 20.3.3 current consumption in power-down mode figure 20-62. power-down supply current vs. v cc (watchdog timer disabled) figure 20-63. power-down supply current vs. v cc (watchdog timer enabled) power-down s upply current v s . s upply voltage watchdog timer di s abled 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 33 .544.555.5 v cc (v) i cc ( u a) power-down s upply current v s . s upply voltage watchdog timer enabled 8 5 c 25 c -40 c 0 2 4 6 8 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 231 8197c?avr?05/11 attiny261a/461a/861a 20.3.4 current consumption in reset figure 20-64. reset supply current vs. low frequency (0.1 - 1.0 mhz, excluding current through the reset pull-up) figure 20-65. reset supply current vs. frequency (1 - 20 mhz, excluding current through the reset pull-up) re s et current v s . frequency excluding current through re s et pullup 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) re s et current v s . s upply voltage excluding current through re s et pullup 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) icc (ma) 232 8197c?avr?05/11 attiny261a/461a/861a 20.3.5 current consumption of peripheral units figure 20-66. analog comparator current vs. v cc figure 20-67. adc current vs. v cc (aref = av cc ) analog comparator current v s . v cc 0 10 20 3 0 40 50 60 70 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) adc current v s . v cc f = 1.0 mhz 0 50 100 150 200 250 3 00 3 50 400 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 233 8197c?avr?05/11 attiny261a/461a/861a figure 20-68. timer/counter1 current vs. v cc figure 20-69. brownout detector current vs. v cc timer/counter1 current v s . v cc 64mhz 3 2mhz 1mhz 0 1000 2000 3 000 4000 5000 6000 7000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) brownout detector current v s . v cc 0 5 10 15 20 25 3 0 3 5 40 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 234 8197c?avr?05/11 attiny261a/461a/861a figure 20-70. programming current vs. v cc 20.3.6 pull-up resistors figure 20-71. pull-up resistor current vs. input voltage (i/o pin, v cc = 1.8v) programming current v s . v cc 0 1000 2000 3 000 4000 5000 6000 7000 8 000 1.5 2 2.5 33 .544.555.5 v cc (v) i cc ( u a) i/o pin pull-up resistor current vs. input voltage v cc = 1.8v 85 ?c 25 ?c -40 ?c 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v op (v) i op (ua) 235 8197c?avr?05/11 attiny261a/461a/861a figure 20-72. pull-up resistor current vs. input voltage (i/o pin, v cc = 3v) figure 20-73. pull-up resistor current vs. input voltage (i/o pin, v cc = 5v) i/o pin pull-up resistor current vs. input voltage v cc = 2.7v 85 ?c 25 ?c -40 ?c 0 10 20 30 40 50 60 70 80 90 0 0,5 1 1,5 2 2,5 3 v op (v) i op (ua) i/o pin pull-up resistor current vs. input voltage v cc = 5v 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 236 8197c?avr?05/11 attiny261a/461a/861a figure 20-74. pull-up resistor current vs. input voltage (reset pin, v cc = 1.8v) figure 20-75. pull-up resistor current vs. input voltage (reset pin, v cc = 3v) re s et pull-up re s i s tor current v s . re s et pin voltage v cc = 1. 8 v 8 5 c 25 c -40 c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v re s et (v) i re s et ( u a) 8 5 c 25 c -40 c re s et pull-up re s i s tor current v s . re s et pin voltage v cc = 3 v 0 10 20 3 0 40 50 60 0 0.5 1 1.5 2 2.5 3 v re s et (v) i re s et ( u a) 237 8197c?avr?05/11 attiny261a/461a/861a figure 20-76. pull-up resistor current vs. input voltage (reset pin, v cc = 5v) 20.3.7 output driver strength figure 20-77. v ol : output voltage vs. sink current (i/o pin, v cc = 1.8v) 8 5 c 25 c -40 c re s et pull-up re s i s tor current v s . re s et pin voltage v cc = 5v 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 33 .5 4 4.5 5 v re s et (v) i re s et ( u a) i/o pin output voltage v s . s ink current v cc = 1. 8 v 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 012 3 45 i ol (ma) v ol (v) 238 8197c?avr?05/11 attiny261a/461a/861a figure 20-78. v ol : output voltage vs. sink current (i/o pin, v cc = 3v) figure 20-79. v ol : output voltage vs. sink current (i/o pin, v cc = 5v) i/o pin output voltage v s . s ink current v cc = 3 v 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 0.45 0246 8 10 i ol (ma) v ol (v) i/o pin output voltage v s . s ink current v cc = 5v 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0 5 10 15 20 i ol (ma) v ol (v) 239 8197c?avr?05/11 attiny261a/461a/861a figure 20-80. v oh : output voltage vs. source current (i/o pin, v cc = 1.8v) figure 20-81. v oh : output voltage vs. source current (i/o pin, v cc = 3v) i/o pin output voltage v s . s ource current v cc = 1. 8 v 8 5 c 25 c -40 c 1.2 1.4 1.6 1. 8 012 3 45 i ol (ma) v ol (v) i/o pin output voltage v s . s ource current v cc = 3 v 8 5 c 25 c -40 c 2.4 2.6 2. 8 3 0246 8 10 i ol (ma) v ol (v) 240 8197c?avr?05/11 attiny261a/461a/861a figure 20-82. v oh : output voltage vs. source current (i/o pin, v cc = 5v) figure 20-83. v ol : output voltage vs. sink current (reset pin as i/o, v cc = 5v) i/o pin output voltage v s . s ource current v cc = 5v 8 5 c 25 c -40 c 4.2 4.4 4.6 4. 8 5 0 5 10 15 20 i ol (ma) v ol (v) output voltage v s . s ink current re s et pin a s i/o, v cc = 5v 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0 0.5 1 1.5 2 2.5 3 i ol (ma) v ol (v) 241 8197c?avr?05/11 attiny261a/461a/861a figure 20-84. v ol : output voltage vs. sink current (reset pin as i/o, t = 25c) figure 20-85. v oh : output voltage vs. source current (reset pin as i/o, v cc = 5v) output voltage v s . s ink current re s et pin a s i/o 1. 8 v 3 .0 v 5.0 v 0 0.1 0.2 0. 3 0.4 0.5 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 i ol (ma) v ol (v) output voltage v s . s ource current re s et pin a s i/o, v cc = 5v 8 5 c 25 c -40 c 0 1 2 3 4 5 0 0.2 0.4 0.6 0. 8 1 i oh (ma) v oh (v) 242 8197c?avr?05/11 attiny261a/461a/861a figure 20-86. v oh : output voltage vs. source current (reset pin as i/o, t = 25c) 20.3.8 input thresholds and hysteresis figure 20-87. v ih : input threshold voltage vs. v cc (i/o pin, read as ?1?) output voltage v s . s ource current re s et pin a s i/o 1. 8 v 3 .0 v 5.0 v 0 1 2 3 4 5 0 0.2 0.4 0.6 0. 8 1 i oh (ma) v oh (v) i/o pin input thre s hold v s . s upply voltage v ih , i/o pin read a s '1' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 243 8197c?avr?05/11 attiny261a/461a/861a figure 20-88. v il : input threshold voltage vs. v cc (i/o pin, read as ?0?) figure 20-89. v ih -v il : input hysteresis vs. v cc (i/o pin) i/o pin input thre s hold v s . s upply voltage v il , i/o pin read a s '0' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .544.555.5 v cc (v) thre s hold (v) i/o pin input hy s tere s i s v s . s upply voltage 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .544.555.5 v cc (v) inp u t hy s tere s i s (v) 244 8197c?avr?05/11 attiny261a/461a/861a figure 20-90. v ih : input threshold voltage vs. v cc (reset pin, read as ?1?) figure 20-91. v il : input threshold voltage vs. v cc (reset pin, read as ?0?) re s et input thre s hold voltage v s . vcc v ih , pin read a s '1' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) re s et input thre s hold voltage v s . vcc v il , pin read a s '0' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 245 8197c?avr?05/11 attiny261a/461a/861a figure 20-92. v ih -v il : input hysteresis vs. v cc (reset pin) 20.3.9 bod, bandgap and reset figure 20-93. bod threshold vs. temperature (bod level set to 4.3v) re s et pin input hy s tere s i s v s . v cc 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) v cc ri s ing v cc falling bod thre s hold s v s . temperature bodlevel = 4. 3 v 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 4. 3 6 4. 38 4.4 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) 246 8197c?avr?05/11 attiny261a/461a/861a figure 20-94. bod threshold vs. temperature (bod level set to 2.7v) figure 20-95. bod threshold vs. temperature (bod level set to 1.8v) v cc ri s ing v cc falling bod thre s hold s v s . temperature bodlevel = 2.7v 2.66 2.6 8 2.7 2.72 2.74 2.76 2.7 8 2. 8 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) bod thre s hold s v s . temperature bodlevel = 1. 8 v v cc ri s ing v cc falling 1.7 8 1.79 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 1. 8 5 1. 8 6 -40 -20 0 20 40 60 8 0 100 temper a t u re (c) thre s hold (v) 247 8197c?avr?05/11 attiny261a/461a/861a figure 20-96. bandgap voltage vs. supply voltage. figure 20-97. minimum reset pulse width vs. v cc bandgap voltage v s . v cc 8 5 c 25 c -40 c 1.07 1.0 8 1.09 1.1 1.11 1.12 1.5 2.5 3 .5 4.5 5.5 v cc (v) b a ndg a p volt a ge (v) minimum re s et pul s e width v s . v cc 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .544.555.5 v cc (v) p u l s ewidth (n s ) 248 8197c?avr?05/11 attiny261a/461a/861a 20.3.10 internal oscillators figure 20-98. frequency of watchd og oscillator vs. v cc figure 20-99. frequency of watc hdog oscillator vs. temperature watchdog o s cillator frequency v s . s upply voltage 8 5 c 25 c -40 c 105000 110000 115000 120000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) fre qu ency (hz) watchdog o s cillator frequency v s . temperature 5.0 v 3 .0 v 1. 8 v 105000 110000 115000 120000 -40 -20 0 20 40 60 8 0100 temper a t u re fre qu ency (khz) 249 8197c?avr?05/11 attiny261a/461a/861a figure 20-100. frequency of calibrated 8.0 mhz oscillator vs. v cc figure 20-101. frequency of calibra ted 8.0 mhz oscillato r vs. temperature calibrated 8 mhz o s cillator frequency v s . s upply voltage 8 5 c 25 c -40 c 7.6 7. 8 8 8 .2 8 .4 1.5 2 2.5 33 .544.555.5 v cc (v) fre qu ency (mhz) calibrated 8 mhz o s cillator frequency v s . s upply voltage 1. 8 v 3 .0 v 5.0 v 7.6 7. 8 8 8 .2 8 .4 -40 -20 0 20 40 60 8 0 100 v cc (v) fre qu ency (mhz) 250 8197c?avr?05/11 attiny261a/461a/861a figure 20-102. frequency of calibra ted 8.0 mhz oscillator vs. osccal value calibrated 8 mhz o s cillator frequency v s . o s ccal value 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 016 3 24 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 o s ccal (x1) fre qu ency (mhz) 251 8197c?avr?05/11 attiny261a/461a/861a 20.4 attiny861a 20.4.1 current consumption in active mode figure 20-103. active supply current vs. low frequency (0.1 - 1.0 mhz) figure 20-104. active supply current vs. frequency (1 - 20 mhz) active s upply current v s . low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.2 0.4 0.6 0. 8 1 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) active s upply current v s . frequency prr = 0xff 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 2 4 6 8 10 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 252 8197c?avr?05/11 attiny261a/461a/861a figure 20-105. active supply current vs. v cc (internal ca librated oscillator, 8 mhz) figure 20-106. active supply current vs. v cc (internal ca librated oscillator, 1 mhz) active s upply current v s . s upply voltage internal o s cillator, 8 mhz 8 5 c 25 c -40 c 0 1 2 3 4 5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) active s upply current v s . s upply voltage internal o s cillator, 1 mhz 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) 253 8197c?avr?05/11 attiny261a/461a/861a figure 20-107. active supply current vs. v cc (internal ca librated oscillator, 128 khz) 20.4.2 current consumption in idle mode figure 20-108. idle supply current vs. low frequency (0.1 - 1.0 mhz) active s upply current v s . s upply voltage internal o s cillator, 12 8 khz 8 5 c 25 c -40 c 0 0.02 0.04 0.06 0.0 8 0.1 0.12 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc (ma) idle s upply current v s . low frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0.14 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) 254 8197c?avr?05/11 attiny261a/461a/861a figure 20-109. idle supply current vs. frequency (1 - 20 mhz) figure 20-110. idle supply current vs. v cc (internal ca librated oscillator, 8 mhz) idle s upply current v s . frequency 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 0 0.5 1 1.5 2 2.5 3 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) i cc (ma) 1. 8 v idle s upply current v s . v cc internal o s cillator, 8 mhz 8 5 c 25 c -40 c 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) icc (ma) 255 8197c?avr?05/11 attiny261a/461a/861a figure 20-111. idle supply current vs. v cc (internal ca librated oscillator, 1 mhz) figure 20-112. idle supply current vs. v cc (internal ca librated oscillator, 128 khz) idle s upply current v s . v cc internal o s cillator, 1 mhz 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (ma) idle s upply current v s . v cc internal o s cillator, 12 8 khz 8 5 c 25 c -40 c 0 0.005 0.01 0.015 0.02 0.025 1.5 2 2.5 33 .544.555.5 v cc (v) i cc (ma) 256 8197c?avr?05/11 attiny261a/461a/861a 20.4.3 current consumption in power-down mode figure 20-113. power-down supply current vs. v cc (watchdog timer disabled) figure 20-114. power-down supply current vs. v cc (watchdog timer enabled) power-down s upply current v s . s upply voltage watchdog timer di s abled 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) power-down s upply current v s . s upply voltage watchdog timer enabled 8 5 c 25 c -40 c 0 2 4 6 8 10 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 257 8197c?avr?05/11 attiny261a/461a/861a 20.4.4 current consumption in reset figure 20-115. reset supply current vs. low frequency (0.1 - 1.0 mhz, excluding current through the reset pull-up) figure 20-116. reset supply current vs. frequency (1 - 20 mhz, excluding current through the reset pull-up) re s et current v s . frequency excluding current through re s et pullup 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.02 0.04 0.06 0.0 8 0.1 0.12 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 fre qu ency (mhz) i cc (ma) re s et current v s . s upply voltage excluding current through re s et pullup 5.5 v 5.0 v 4.5 v 4.0 v 3 . 3 v 2.7 v 1. 8 v 0 0.5 1 1.5 2 2.5 0246 8 10 12 14 16 1 8 20 fre qu ency (mhz) icc (ma) 258 8197c?avr?05/11 attiny261a/461a/861a 20.4.5 current consumption of peripheral units figure 20-117. analog comparator current vs. v cc figure 20-118. adc current vs. v cc (aref = av cc ) analog comparator current v s . v cc 0 10 20 3 0 40 50 60 70 8 0 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) adc current v s . v cc f = 1.0 mhz 0 50 100 150 200 250 3 00 3 50 400 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 259 8197c?avr?05/11 attiny261a/461a/861a figure 20-119. timer/counter1 current vs. v cc figure 20-120. brownout detector current vs. v cc timer/counter1 current v s . v cc 64mhz 3 2mhz 1mhz 0 1000 2000 3 000 4000 5000 6000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) brownout detector current v s . v cc 0 5 10 15 20 25 3 0 3 5 40 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) 260 8197c?avr?05/11 attiny261a/461a/861a figure 20-121. programming current vs. v cc 20.4.6 pull-up resistors figure 20-122. pull-up resistor current vs. input voltage (i/o pin, v cc = 1.8v) programming current v s . v cc 0 2000 4000 6000 8 000 10000 12000 14000 16000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) i cc ( u a) i/o pin pull-up resistor current vs. input voltage v cc = 1.8v 85 ?c 25 ?c -40 ?c 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 v op (v) i op (ua) 261 8197c?avr?05/11 attiny261a/461a/861a figure 20-123. pull-up resistor current vs. input voltage (i/o pin, v cc = 3v) figure 20-124. pull-up resistor current vs. input voltage (i/o pin, v cc = 5v) i/o pin pull-up resistor current vs. input voltage v cc = 2.7v 85 ?c 25 ?c -40 ?c 0 10 20 30 40 50 60 70 80 90 0 0,5 1 1,5 2 2,5 3 v op (v) i op (ua) i/o pin pull-up resistor current vs. input voltage v cc = 5v 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 262 8197c?avr?05/11 attiny261a/461a/861a figure 20-125. pull-up resistor current vs. input voltage (reset pin, v cc = 1.8v) figure 20-126. pull-up resistor current vs. input voltage (reset pin, v cc = 3v) re s et pull-up re s i s tor current v s . re s et pin voltage v cc = 1. 8 v 8 5 c 25 c -40 c 0 5 10 15 20 25 3 0 3 5 40 0 0.2 0.4 0.6 0. 8 1 1.2 1.4 1.6 1. 8 2 v re s et (v) i re s et ( u a) 8 5 c 25 c -40 c re s et pull-up re s i s tor current v s . re s et pin voltage v cc = 3 v 0 10 20 3 0 40 50 60 00.511.522.5 3 v re s et (v) i re s et ( u a) 263 8197c?avr?05/11 attiny261a/461a/861a figure 20-127. pull-up resistor current vs. input voltage (reset pin, v cc = 5v) 20.4.7 output driver strength figure 20-128. v ol : output voltage vs. sink current (i/o pin, v cc = 1.8v) 8 5 c 25 c -40 c re s et pull-up re s i s tor current v s . re s et pin voltage v cc = 5v 0 20 40 60 8 0 100 120 0 0.5 1 1.5 2 2.5 33 .5 4 4.5 5 v re s et (v) i re s et ( u a) i/o pin output voltage v s . s ink current v cc = 1. 8 v 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 012 3 45 i ol (ma) v ol (v) 264 8197c?avr?05/11 attiny261a/461a/861a figure 20-129. v ol : output voltage vs. sink current (i/o pin, v cc = 3v) figure 20-130. v ol : output voltage vs. sink current (i/o pin, v cc = 5v) i/o pin output voltage v s . s ink current v cc = 3 v 8 5 c 25 c -40 c 0 0.05 0.1 0.15 0.2 0.25 0. 3 0. 3 5 0.4 0246 8 10 i ol (ma) v ol (v) i/o pin output voltage v s . s ink current v cc = 5v 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0 5 10 15 20 i ol (ma) v ol (v) 265 8197c?avr?05/11 attiny261a/461a/861a figure 20-131. v oh : output voltage vs. source current (i/o pin, v cc = 1.8v) figure 20-132. v oh : output voltage vs. source current (i/o pin, v cc = 3v) i/o pin output voltage v s . s ource current v cc = 1. 8 v 8 5 c 25 c -40 c 1.2 1.4 1.6 1. 8 012 3 45 i ol (ma) v ol (v) i/o pin output voltage v s . s ource current v cc = 3 v 8 5 c 25 c -40 c 2.4 2.6 2. 8 3 0246 8 10 i ol (ma) v ol (v) 266 8197c?avr?05/11 attiny261a/461a/861a figure 20-133. v oh : output voltage vs. source current (i/o pin, v cc = 5v) figure 20-134. v ol : output voltage vs. sink current (reset pin as i/o, v cc = 5v) i/o pin output voltage v s . s ource current v cc = 5v 8 5 c 25 c -40 c 4.2 4.4 4.6 4. 8 5 0 5 10 15 20 i ol (ma) v ol (v) output voltage v s . s ink current re s et pin a s i/o, v cc = 5v 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0 0.5 1 1.5 2 2.5 3 i ol (ma) v ol (v) 267 8197c?avr?05/11 attiny261a/461a/861a figure 20-135. v ol : output voltage vs. sink current (reset pin as i/o, t = 25c) figure 20-136. v oh : output voltage vs. source current (reset pin as i/o, v cc = 5v) output voltage v s . s ink current re s et pin a s i/o 1. 8 v 3 .0 v 5.0 v 0 0.1 0.2 0. 3 0.4 0.5 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 i ol (ma) v ol (v) output voltage v s . s ource current re s et pin a s i/o, v cc = 5v 8 5 c 25 c -40 c 0 1 2 3 4 5 0 0.2 0.4 0.6 0. 8 1 i oh (ma) v oh (v) 268 8197c?avr?05/11 attiny261a/461a/861a figure 20-137. v oh : output voltage vs. source current (reset pin as i/o, t = 25c) 20.4.8 input thresholds and hysteresis figure 20-138. v ih : input threshold voltage vs. v cc (i/o pin, read as ?1?) output voltage v s . s ource current re s et pin a s i/o 1. 8 v 3 .0 v 5.0 v 0 1 2 3 4 5 0 0.2 0.4 0.6 0. 8 1 i oh (ma) v oh (v) i/o pin input thre s hold v s . s upply voltage v ih , i/o pin read a s '1' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 3 .5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 269 8197c?avr?05/11 attiny261a/461a/861a figure 20-139. v il : input threshold voltage vs. v cc (i/o pin, read as ?0?) figure 20-140. v ih -v il : input hysteresis vs. v cc (i/o pin) i/o pin input thre s hold v s . s upply voltage v il , i/o pin read a s '0' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) i/o pin input hy s tere s i s v s . s upply voltage 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) 270 8197c?avr?05/11 attiny261a/461a/861a figure 20-141. v ih : input threshold voltage vs. v cc (reset pin, read as ?1?) figure 20-142. v il : input threshold voltage vs. v cc (reset pin, read as ?0?) re s et input thre s hold voltage v s . vcc v ih , pin read a s '1' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .544.555.5 v cc (v) thre s hold (v) re s et input thre s hold voltage v s . vcc v il , pin read a s '0' 8 5 c 25 c -40 c 0 0.5 1 1.5 2 2.5 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) thre s hold (v) 271 8197c?avr?05/11 attiny261a/461a/861a figure 20-143. v ih -v il : input hysteresis vs. v cc (reset pin) 20.4.9 bod, bandgap and reset figure 20-144. bod threshold vs. temperature (bod level set to 4.3v) re s et pin input hy s tere s i s v s . v cc 8 5 c 25 c -40 c 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.9 1 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) inp u t hy s tere s i s (v) v cc ri s ing v cc falling bod thre s hold s v s . temperature bodlevel = 4. 3 v 4.22 4.24 4.26 4.2 8 4. 3 4. 3 2 4. 3 4 4. 3 6 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) 272 8197c?avr?05/11 attiny261a/461a/861a figure 20-145. bod threshold vs. temperature (bod level set to 2.7v) figure 20-146. bod threshold vs. temperature (bod level set to 1.8v) v cc ri s ing v cc falling bod thre s hold s v s . temperature bodlevel = 2.7v 2.66 2.6 8 2.7 2.72 2.74 2.76 2.7 8 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) bod thre s hold s v s . temperature bodlevel = 1. 8 v v cc ri s ing v cc falling 1.7 8 1.79 1. 8 1. 8 1 1. 8 2 1. 83 1. 8 4 -40 -20 0 20 40 60 8 0100 temper a t u re (c) thre s hold (v) 273 8197c?avr?05/11 attiny261a/461a/861a figure 20-147. bandgap voltage vs. supply voltage. figure 20-148. minimum reset pulse width vs. v cc bandgap voltage v s . v cc 8 5 c 25 c -40 c 1.07 1.0 8 1.09 1.1 1.11 1.5 2.5 3 .5 4.5 5.5 v cc (v) b a ndg a p volt a ge (v) minimum re s et pul s e width v s . v cc 8 5 c 25 c -40 c 0 200 400 600 8 00 1000 1200 1400 1600 1 8 00 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) p u l s ewidth (n s ) 274 8197c?avr?05/11 attiny261a/461a/861a 20.4.10 internal oscillators figure 20-149. frequency of watchd og oscillator vs. v cc figure 20-150. frequency of watc hdog oscillator vs. temperature watchdog o s cillator frequency v s . s upply voltage 8 5 c 25 c -40 c 100000 105000 110000 115000 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) fre qu ency (hz) watchdog o s cillator frequency v s . temperature 5.0 v 3 .0 v 1. 8 v 100000 105000 110000 115000 -40 -20 0 20 40 60 8 0 100 temper a t u re fre qu ency (khz) 275 8197c?avr?05/11 attiny261a/461a/861a figure 20-151. frequency of calibrated 8.0 mhz oscillator vs. v cc figure 20-152. frequency of calibra ted 8.0 mhz oscillato r vs. temperature calibrated 8 mhz o s cillator frequency v s . s upply voltage 8 5 c 25 c -40 c 7.6 7. 8 8 8 .2 8 .4 1.5 2 2.5 33 .5 4 4.5 5 5.5 v cc (v) fre qu ency (mhz) calibrated 8 mhz o s cillator frequency v s . s upply voltage 1. 8 v 3 .0 v 5.0 v 7.6 7. 8 8 8 .2 8 .4 -40 -20 0 20 40 60 8 0100 v cc (v) fre qu ency (mhz) 276 8197c?avr?05/11 attiny261a/461a/861a figure 20-153. frequency of calibra ted 8.0 mhz oscillator vs. osccal value calibrated 8 mhz o s cillator frequency v s . o s ccal value 8 5 c 25 c -40 c 0 2 4 6 8 10 12 14 016 3 24 8 64 8 0 96 112 12 8 144 160 176 192 20 8 224 240 o s ccal (x1) frc (mhz) 277 8197c?avr?05/11 attiny261a/461a/861a 21. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c page 8 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 page 11 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 11 0x3c (0x5c) reserved ? 0x3b (0x5b) gimsk int1 int0 pcie1 pcie0 ? ? ? ? page 51 0x3a (0x5a) gifr intf1 intf0 pcif ? ? ? ? ? page 52 0x39 (0x59) timsk ocie1d ocie1a ocie1b ocie0a ocie0b toie1 toie0 ticie0 page 85 , page 122 0x38 (0x58) tifr ocf1d ocf1a oc f1b ocf0a ocf0b tov1 tov0 icf0 page 86 , page 122 0x37 (0x57) spmcsr ? ? ? ctpb rflb pgwrt pgers spmen page 167 0x36 (0x56) prr ? ? ? ? prtim1 prtim0 prusi pradc page 36 0x35 (0x55) mcucr bods pud se sm1 sm0 bodse isc01 isc00 page 38 , page 68 , page 51 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf page 46 , 0x33 (0x53) tccr0b ? ? ? tsm psr0 cs02 cs01 cs00 page 84 0x32 (0x52) tcnt0l timer/counter0 counter register low byte page 84 0x31 (0x51) osccal oscillat or calibration register page 32 0x30 (0x50) tccr1a com1a1 com1a0 com1b1 com1b0 foc1a foc1b pwm1a pwm1b page 111 0x2f (0x4f) tccr1b pwm1x psr1 dtps11 dtps10 cs13 cs12 cs11 cs10 page 167 0x2e (0x4e) tcnt1 timer/counter1 counter register page 120 0x2d (0x4d) ocr1a timer/counter1 output compare register a page 120 0x2c (0x4c) ocr1b timer/counter1 output compare register b page 121 0x2b (0x4b) ocr1c timer/counter1 output compare register c page 121 0x2a (0x4a) ocr1d timer/counter1 output compare register d page 121 0x29 (0x49) pllcsr lsm pcke plle plock page 119 0x28 (0x48) clkpr clkpce clkps3 clkps2 clkps1 clkps0 page 32 0x27 (0x47) tccr1c com1a1s com1a0s co m1b1s com1b0s com1d1 com1d0 foc1d pwm1d page 116 0x26 (0x46) tccr1d fpie1 fpen1 fpnc1 fpes1 fpac1 fpf1 wgm11 wgm10 page 117 0x25 (0x45) tc1h ? ? ? ? ? ? tc19 tc18 page 120 0x24 (0x44) dt1 dt1h3 dt1h2 dt1h1 dt1h0 dt1l3 dt1l2 dt1l1 dt1l0 page 123 0x23 (0x43) pcmsk0 pcint7 pcint6 pcin t5 pcint4 pcint3 pcint2 pcint1 pcint0 page 53 0x22 (0x42) pcmsk1 pcint15 pcint14 pcin t13 pcint12 pcint11 pcint10 pcint9 pcint8 page 53 0x21 (0x41) wdtcr wdif wdi e wdp3 wdce wde wdp2 wdp1 wdp0 page 46 0x20 (0x40) dwdr dwdr[7:0] page 36 0x1f (0x3f) eearh ? ? ? ? ? ? ?eear8 page 20 0x1e (0x3e) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 21 0x1d (0x3d) eedr eeprom data register page 21 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere page 21 0x1b (0x3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 68 0x1a (0x3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 68 0x19 (0x39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 69 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 69 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 69 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 69 0x15 (0x35) tccr0a tcw0 icen0 icnc0 ices0 acic0 ? ?ctc0 page 83 0x14 (0x34) tcnt0h timer/counter0 counter register high byte page 85 0x13 (0x33) ocr0a timer/counter0 output compare register a page 85 0x12 (0x32) ocr0b timer/counter0 output compare register b page 85 0x11 (0x31) usipp ? ? ? ? ? ? ?usipos page 135 0x10 (0x30) usibr usi buffer register page 132 0x0f (0x2f) usidr usi data register page 131 0x0e (0x2e) usisr usisif usioif usipf u sidc usicnt3 usicnt2 usicnt1 usicnt0 page 132 0x0d (0x2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc page 133 0x0c (0x2c) gpior2 general purpose i/o register 2 page 23 0x0b (0x2b) gpior1 general purpose i/o register 1 page 23 0x0a (0x2a) gpior0 general purpose i/o register 0 page 23 0x09 (0x29) acsrb hsel hlev ? ? ? acm2 acm1 acm0 page 139 0x08 (0x28) acsra acd acbg aco aci acie acme acis1 acis0 page 138 0x07 (0x27) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 155 0x06 (0x26) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 154 0x05 (0x25) adch adc data register high byte page 155 0x04 (0x24) adcl adc data register low byte page 155 0x03 (0x23) adcsrb bin gsel ? refs2 mux5 adts2 adts1 adts0 page 159 0x02 (0x22) didr1 adc1 0d adc9d adc8d adc7d ? ? ? ? page 160 0x01 (0x21) didr0 adc6d adc5d adc 4d adc3d arefd adc2d adc1d adc0d page 160 0x00 (0x20) tccr1e ? ? oc1oe5 oc1oe4 oc1oe3 oc1oe2 oc1oe1 oc1oe0 page 118 278 8197c?avr?05/11 attiny261a/461a/861a note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operation the specified bit, and can theref ore be used on registers contai ning such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 279 8197c?avr?05/11 attiny261a/461a/861a 22. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 280 8197c?avr?05/11 attiny261a/461a/861a asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 281 8197c?avr?05/11 attiny261a/461a/861a 23. ordering information notes: 1. code indicators: ? n or u: matte tin ? r: tape & reel 2. all packages are pb-free, halide-free and fully green and they comply with the european directive for restriction of hazard- ous substances (rohs). 3. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 4. for typical and electrical characteristics of this device please consult ?appendix a ? attiny261a specification at 105 c?. 23.1 attiny261a speed (mhz) power supply ordering code (1) package (2) operational range 20 1.8 ? 5.5v attiny261a-mu attiny261a-mur attiny261a-pu attiny261a-su attiny261a-sur attiny261a-xu attiny261a-xur 32m1-a 32m1-a 20p3 20s2 20s2 20x 20x industrial (-40 c to +85 c) (3) 20 1.8 ? 5.5v attiny261a-mn attiny261a-mnr 32m1-a 32m1-a industrial (-40 c to +105 c) (4) package type 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (soic) 20x 20-lead, 4.4 mm wide, plastic thin shrink small outline package (tssop) 282 8197c?avr?05/11 attiny261a/461a/861a notes: 1. code indicators: ? u: matte tin ? r: tape & reel 2. all packages are pb-free, halide-free and fully green and they comply with the european directive for restriction of hazard- ous substances (rohs). 3. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 23.2 attiny461a speed (mhz) power supply ordering code (1) package (2) operational range 20 1.8 ? 5.5v attiny461a-mu attiny461a-mur attiny461a-pu attiny461a-su attiny461a-sur attiny461a-xu attiny461a-xur 32m1-a 32m1-a 20p3 20s2 20s2 20x 20x industrial (-40 c to +85 c) (3) package type 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0. 50 mm, micro lead frame package (mlf) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (soic) 20x 20-lead, 4.4 mm wide, plastic thin shrink small outline package (tssop) 283 8197c?avr?05/11 attiny261a/461a/861a notes: 1. code indicators: ? u: matte tin ? r: tape & reel 2. all packages are pb-free, halide-free and fully green and they comply with the european directive for restriction of hazard- ous substances (rohs). 3. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 23.3 attiny861a speed (mhz) power supply ordering code (1) package (2) operational range 20 1.8 ? 5.5v attiny861a-mu attiny861a-mur attiny861a-pu attiny861a-su attiny861a-sur attiny861a-xu attiny861a-xur 32m1-a 32m1-a 20p3 20s2 20s2 20x 20x industrial (-40 c to +85 c) (3) package type 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0. 50 mm, micro lead frame package (mlf) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s2 20-lead, 0.300" wide, plastic gull wing small outline package (soic) 20x 20-lead, 4.4 mm wide, plastic thin shrink small outline package (tssop) 284 8197c?avr?05/11 attiny261a/461a/861a 24. packaging information 24.1 32m1-a 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 3 2m1-a , 3 2-p a d, 5 x 5 x 1.0 mm body, le a d pitch 0.50 mm, e 3 2m1-a 5/25/06 3 .10 mm expo s ed p a d, micro le a d fr a me p a ck a ge (mlf) common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note d1 d e1 e e b a 3 a2 a1 a d2 e2 0.0 8 c l 1 2 3 p p 0 1 2 3 a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a 3 0.20 ref b 0.1 8 0.2 3 0. 3 0 d d1 d2 2.95 3 .10 3 .25 4.90 5.00 5.10 4.70 4.75 4. 8 0 4.70 4.75 4. 8 0 4.90 5.00 5.10 e e1 e2 2.95 3 .10 3 .25 e 0.50 b s c l 0. 3 0 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec s t a nd a rd mo-220, fig. 2 (anvil s ing u l a tion), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k 285 8197c?avr?05/11 attiny261a/461a/861a 24.2 20p3 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. r rev. 20p 3 , 20-le a d (0. 3 00"/7.62 mm wide) pl as tic d ua l inline p a ck a ge (pdip) d 20p 3 2010-10-19 pin 1 e1 a1 b e b1 c l s eating plane a d e eb ec common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a ? ? 5. 33 4 a1 0. 38 1 ? ? d 25.49 3 ? 25.9 8 4 note 2 e 7.620 ? 8 .255 e1 6.096 ? 7.112 note 2 b 0. 3 56 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3 . 8 10 c 0.20 3 ? 0. 3 56 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ note s : 1. thi s p a ck a ge conform s to jedec reference m s -001, v a ri a tion ad. 2. dimen s ion s d a nd e1 do not incl u de mold fl as h or protr us ion. mold fl as h or protr us ion s h a ll not exceed 0.25 mm (0.010"). 286 8197c?avr?05/11 attiny261a/461a/861a 24.3 20s2 287 8197c?avr?05/11 attiny261a/461a/861a 24.4 20x 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20x , (formerly 20t), 20-lead, 4.4 mm body width, plastic thin shrink small outline package (tssop) c 20x 10/23/03 6.60 (.260) 6.40 (.252) 1.20 (0.047) max 0.65 (.0256) bsc 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) index mark 6.50 (0.256) 6.25 (0.246) seating plane 4.50 (0.177) 4.30 (0.169) pin 1 0.75 (0.030) 0.45 (0.018) 0o ~ 8o 0.30 (0.012) 0.19 (0.007) dimensions in millimeters and (inches). controlling dimension: millimeters. jedec standard mo-153 ac 288 8197c?avr?05/11 attiny261a/461a/861a 25. errata 25.1 errata attiny261a the revision letter in this section refers to the revision of the attiny261a device. 25.1.1 rev d no known errata. 25.1.2 rev c not sampled. 25.2 errata attiny461a the revision letter in this section refers to the revision of the attiny461a device. 25.2.1 rev c no known errata. 25.3 errata attiny861a the revision letter in this section refers to the revision of the attiny861a device. 25.3.1 rev d no known errata. 25.3.2 rev c not sampled. 289 8197c?avr?05/11 attiny261a/461a/861a 26. datasheet revision history 26.1 rev. 8197c ? 05/11 1. added: ? section 3.3 ?capacitive touch sensing? on page 6 ? section 4. ?cpu core? on page 7 ? table 6-10, ?capacitance of low-freq uency crystal oscillator,? on page 29 ? table 15-5 on page 157 ? section 19.7 ?analog comparator characteristics? on page 193 ? table 19-8 on page 191 ? table 19-9 on page 192 ? tape & reel part numbers in section 23. ?ordering information? on page 281 ? ordering codes for attiny261a with extended temperature, on page 281 2. updated: ? section 6.4 ?clock output buffer? on page 32 (clko) ? figure 15-1 on page 142 , ?analog to digital converter block schematic?, changed internal 1.18v reference to 1.1v ? table 18-8 on page 171 , no. of pages in the eeprom from 64 to 32 for attiny261a ? table 19-1 on page 185 ? section 19.3 ?speed? on page 187 ? characteristic plots figure 20-3 on page 200 , figure 20-8 on page 202 , figure 20- 54 on page 226 , figure 20-59 on page 228 , figure 20-105 on page 252 , and figure 20-110 on page 254 ? bit syntax throughout the datasheet, e.g. from cs02:0 to cs0[2:0] 3. deleted: ? ?preliminary? status. all devices now final and in production. ? ?disclaimer? on page 6 . 26.2 rev. 8197b ? 01/10 1. updated 32m1-a drawing in section 24. ?packaging information? on page 284 . 26.3 rev. 8197a ? 10/09 1. initial revision created from document 2588c (attiny261/461/861) 2. updated "ordering information" on page 281 , page 282 and page 283 . pb-plated pack- ages are no longer offered and there are no separate ordering codes for commercial operation range, the only available option now is industrial. also, added new package options 3. added sections: ? ?software bod disable? on page 36 ? ?attiny461a? on page 225 ? ?attiny861a? on page 251 4. updated sections: ? ?stack pointer? on page 11 290 8197c?avr?05/11 attiny261a/461a/861a ? ?osccal ? oscillator calibra tion register? on page 32 ? ?mcucr ? mcu control register? on page 38 ? ?mcucr ? mcu control register? on page 51 ? ?mcucr ? mcu control register? on page 68 ? ?speed? on page 187 ? ?enhanced power-on reset? on page 189 ? ?attiny261a? on page 199 ? ?register summary? on page 277 5. updated tables: ? ?dc characteristics. ta = -40c to +85c, vcc = 1.8v to 5.5v (unless otherwise noted).? on page 185 ? ?additional current consumption for the different i/o modules (absolute values).? on page 197 ? ?additional current consumption (percentage) in active and idle mode.? on page 198 i 8197c?avr?05/11 attiny261a/461a/861a table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations ..... ................ ................. ................ ................. ............ 2 1.1 pin descriptions .................................................................................................3 2 overview ............ ................ ................ ............... .............. .............. ............ 4 2.1 block diagram ...................................................................................................4 3 general information ............ .............. ............... .............. .............. ............ 6 3.1 resources .........................................................................................................6 3.2 code examples .................................................................................................6 3.3 capacitive touch sensing .................................................................................6 3.4 data retention ...................................................................................................6 4cpu core ............... .............. .............. ............... .............. .............. ............ 7 4.1 architectural overview .......................................................................................7 4.2 alu ? arithmetic logic unit ...............................................................................8 4.3 status register ..................................................................................................8 4.4 general purpose register file ........................................................................10 4.5 stack pointer ...................................................................................................11 4.6 instruction execution timing ...........................................................................12 4.7 reset and interrupt handling ...........................................................................12 5 memories ............... .............. .............. ............... .............. .............. .......... 15 5.1 in-system re-programmable flash program memory ....................................15 5.2 sram data memory ........................................................................................15 5.3 eeprom data memory . ................. ................ ............. ............ ............. ..........16 5.4 i/o memory ......................................................................................................20 5.5 register description ........................................................................................20 6 clock system ........... ................ ................ ................. ................ ............. 24 6.1 clock subsystems ...........................................................................................24 6.2 clock sources .................................................................................................25 6.3 system clock prescaler ..................................................................................31 6.4 clock output buffer .........................................................................................32 6.5 register description ........................................................................................32 7 power management and sleep mo des ............... .............. ............ ........ 35 7.1 sleep modes ....................................................................................................35 ii 8197c?avr?05/11 attiny261a/461a/861a 7.2 software bod disable .....................................................................................36 7.3 power reduction register ...............................................................................37 7.4 minimizing power consumption ......................................................................37 7.5 register description ........................................................................................38 8 system control and reset ...... ................ ................. ................ ............. 40 8.1 resetting the avr ...........................................................................................40 8.2 reset sources .................................................................................................41 8.3 internal voltage reference ..............................................................................43 8.4 watchdog timer ..............................................................................................43 8.5 register description ........................................................................................46 9 interrupts ........ ................. ................ ................. .............. .............. .......... 49 9.1 interrupt vectors ..............................................................................................49 9.2 external interrupts ...........................................................................................50 9.3 register description ........................................................................................51 10 i/o ports ............... ................ .............. ............... .............. .............. .......... 54 10.1 ports as general digital i/o .............................................................................55 10.2 alternate port functions ..................................................................................59 10.3 register description ........................................................................................68 11 timer/counter0 ............... ................ ................. .............. .............. .......... 70 11.1 features ..........................................................................................................70 11.2 overview ..........................................................................................................70 11.3 clock sources .................................................................................................71 11.4 counter unit ....................................................................................................73 11.5 input capture unit ...........................................................................................74 11.6 output compare unit .......................................................................................75 11.7 modes of operation .........................................................................................76 11.8 timer/counter timing diagrams .....................................................................78 11.9 accessing registers in 16-bit mode ................................................................79 11.10 register description ........................................................................................83 12 timer/counter1 ............... ................ ................. .............. .............. .......... 88 12.1 features ..........................................................................................................88 12.2 overview ..........................................................................................................88 12.3 clock sources .................................................................................................91 12.4 counter unit ....................................................................................................92 iii 8197c?avr?05/11 attiny261a/461a/861a 12.5 output compare unit .......................................................................................93 12.6 dead time generator ......................................................................................95 12.7 compare match output unit ............................................................................96 12.8 modes of operation .........................................................................................98 12.9 timer/counter timing diagrams ...................................................................105 12.10 fault protection unit ......................................................................................106 12.11 accessing 10-bit registers ............................................................................107 12.12 register description ......................................................................................111 13 usi ? universal seri al interface ............ ................. ................ ............. 124 13.1 features ........................................................................................................124 13.2 overview ........................................................................................................124 13.3 functional descriptions .................................................................................125 13.4 alternative usi usage ...................................................................................130 13.5 register descriptions ....................................................................................131 14 ac ? analog comparator ... .............. ............... .............. .............. ........ 136 14.1 analog comparator multiplexed input ...........................................................136 14.2 register description ......................................................................................138 15 adc ? analog to digital co nverter .............. .............. .............. ........... 141 15.1 features ........................................................................................................141 15.2 overview ........................................................................................................141 15.3 operation .......................................................................................................142 15.4 starting a conversion ....................................................................................143 15.5 prescaling and conversion timing ................................................................144 15.6 changing channel or reference selection ...................................................147 15.7 adc noise canceler .....................................................................................148 15.8 analog input circuitry ....................................................................................148 15.9 noise canceling techniques .........................................................................149 15.10 adc accuracy definitions .............................................................................149 15.11 adc conversion result .................................................................................152 15.12 temperature measurement ...........................................................................153 15.13 register description ......................................................................................154 16 debugwire on-chip debug s ystem .............. .............. .............. ........ 161 16.1 features ........................................................................................................161 16.2 overview ........................................................................................................161 16.3 physical interface ..........................................................................................161 iv 8197c?avr?05/11 attiny261a/461a/861a 16.4 software break points ...................................................................................162 16.5 limitations of debugwire .............................................................................162 16.6 register description ......................................................................................162 17 self-programming the flash .. ............... ................. ................ ............. 163 17.1 performing page erase by spm ....................................................................163 17.2 filling the temporary buffer (page loading) .................................................163 17.3 performing a page write ...............................................................................164 17.4 addressing the flash during self-programming ...........................................164 17.5 eeprom write prevents writing to spmcsr ............. ............ ............. ........165 17.6 reading fuse and lock bits from software ..................................................165 17.7 preventing flash corruption ..........................................................................166 17.8 programming time for flash when using spm ............................................166 17.9 register description ......................................................................................167 18 memory programming ........ .............. ............... .............. .............. ........ 168 18.1 program and data memory lock bits ...........................................................168 18.2 fuse bytes .....................................................................................................169 18.3 signature bytes .............................................................................................170 18.4 calibration byte .............................................................................................170 18.5 page size ......................................................................................................171 18.6 serial programming .......................................................................................171 18.7 parallel programming ....................................................................................175 19 electrical characteristics ... .............. ............... .............. .............. ........ 185 19.1 absolute maximum ratings* .........................................................................185 19.2 dc characteristics .........................................................................................185 19.3 speed ............................................................................................................187 19.4 clock characteristics .....................................................................................187 19.5 system and reset characteristics ................................................................188 19.6 adc characteristics ......................................................................................190 19.7 analog comparator characteristics ...............................................................193 19.8 serial programming characteristics ..............................................................193 19.9 parallel programming characteristics ...........................................................194 20 typical characteristics ....... .............. ............... .............. .............. ........ 197 20.1 supply current of i/o modules ......................................................................197 20.2 attiny261a ....................................................................................................199 20.3 attiny461a ....................................................................................................225 v 8197c?avr?05/11 attiny261a/461a/861a 20.4 attiny861a ....................................................................................................251 21 register summary ............ .............. .............. .............. .............. ........... 277 22 instruction set summary ... .............. ............... .............. .............. ........ 279 23 ordering information .......... .............. ............... .............. .............. ........ 281 23.1 attiny261a ....................................................................................................281 23.2 attiny461a ....................................................................................................282 23.3 attiny861a ....................................................................................................283 24 packaging information .......... ................ ................. ................ ............. 284 24.1 32m1-a ..........................................................................................................284 24.2 20p3 ..............................................................................................................285 24.3 20s2 ..............................................................................................................286 24.4 20x ................................................................................................................287 25 errata ........... ................ ................ ................. ................ .............. ........... 288 25.1 errata attiny261a .........................................................................................288 25.2 errata attiny461a .........................................................................................288 25.3 errata attiny861a .........................................................................................288 26 datasheet revision history .. ................ ................. ................ ............. 289 26.1 rev. 8197c ? 05/11 .......................................................................................289 26.2 rev. 8197b ? 01/10 .......................................................................................289 26.3 rev. 8197a ? 10/09 .......................................................................................289 table of contents.......... ................. ................ ................. ................ ........... i 8197c?avr?05/11 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: (+1)(408) 441-0311 fax: (+1)(408) 487-2600 atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (+81)(3) 3523-3551 fax: (+81)(3) 3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2011 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others ar e registered trademarks or trademarks of at mel corporation or its subsidiaries. o ther terms and product names may be trademarks of others. |
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